branch.hh (7149:97666c2fc7a5) branch.hh (7153:6ce0bf0ddaf3)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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41 */
42#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
43#define __ARCH_ARM_INSTS_BRANCH_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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41 */
42#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
43#define __ARCH_ARM_INSTS_BRANCH_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49/**
50 * Base class for instructions whose disassembly is not purely a
51 * function of the machine instruction (i.e., it depends on the
52 * PC). This class overrides the disassemble() method to check
53 * the PC and symbol table values before re-using a cached
54 * disassembly string. This is necessary for branches and jumps,
55 * where the disassembly string includes the target address (which
56 * may depend on the PC and/or symbol table).
57 */
58class PCDependentDisassembly : public PredOp
59{
60 protected:
61 /// Cached program counter from last disassembly
62 mutable Addr cachedPC;
63
64 /// Cached symbol table pointer from last disassembly
65 mutable const SymbolTable *cachedSymtab;
66
67 /// Constructor
68 PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
69 OpClass __opClass)
70 : PredOp(mnem, _machInst, __opClass),
71 cachedPC(0), cachedSymtab(0)
72 {
73 }
74
75 const std::string &
76 disassemble(Addr pc, const SymbolTable *symtab) const;
77};
78
79// Branch to a target computed with an immediate
80class BranchImm : public PredOp
81{
82 protected:
83 int32_t imm;
84
85 public:
86 BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,

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155
156 public:
157 BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
158 int32_t _imm, IntRegIndex _op1) :
159 PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
160 {}
161};
162
49// Branch to a target computed with an immediate
50class BranchImm : public PredOp
51{
52 protected:
53 int32_t imm;
54
55 public:
56 BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,

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125
126 public:
127 BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
128 int32_t _imm, IntRegIndex _op1) :
129 PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
130 {}
131};
132
163/**
164 * Base class for branches (PC-relative control transfers),
165 * conditional or unconditional.
166 */
167class Branch : public PCDependentDisassembly
168{
169 protected:
170 /// target address (signed) Displacement .
171 int32_t disp;
172
173 /// Constructor.
174 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
175 : PCDependentDisassembly(mnem, _machInst, __opClass),
176 disp(machInst.offset << 2)
177 {
178 //If Bit 26 is 1 then Sign Extend
179 if ( (disp & 0x02000000) > 0 ) {
180 disp |= 0xFC000000;
181 }
182 }
183
184 Addr branchTarget(Addr branchPC) const;
185
186 std::string
187 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
188};
189
190/**
191 * Base class for branch and exchange instructions on the ARM
192 */
193class BranchExchange : public PredOp
194{
195 protected:
196 /// Constructor
197 BranchExchange(const char *mnem, ExtMachInst _machInst,
198 OpClass __opClass)
199 : PredOp(mnem, _machInst, __opClass)
200 {
201 }
202
203 std::string
204 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
205};
206
207}
208
209#endif //__ARCH_ARM_INSTS_BRANCH_HH__
133}
134
135#endif //__ARCH_ARM_INSTS_BRANCH_HH__