1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University |
15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the --- 48 unchanged lines hidden (view full) --- 71 cachedPC(0), cachedSymtab(0) 72 { 73 } 74 75 const std::string & 76 disassemble(Addr pc, const SymbolTable *symtab) const; 77}; 78 |
79// Branch to a target computed with an immediate 80class BranchImm : public PredOp 81{ 82 protected: 83 int32_t imm; 84 85 public: 86 BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 87 int32_t _imm) : 88 PredOp(mnem, _machInst, __opClass), imm(_imm) 89 {} 90}; 91 92// Conditionally Branch to a target computed with an immediate 93class BranchImmCond : public BranchImm 94{ 95 protected: 96 // This will mask the condition code stored for PredOp. Ideally these two 97 // class would cooperate, but they're not set up to do that at the moment. 98 ConditionCode condCode; 99 100 public: 101 BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 102 int32_t _imm, ConditionCode _condCode) : 103 BranchImm(mnem, _machInst, __opClass, _imm), condCode(_condCode) 104 {} 105}; 106 107// Branch to a target computed with a register 108class BranchReg : public PredOp 109{ 110 protected: 111 IntRegIndex op1; 112 113 public: 114 BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 115 IntRegIndex _op1) : 116 PredOp(mnem, _machInst, __opClass), op1(_op1) 117 {} 118}; 119 120// Conditionally Branch to a target computed with a register 121class BranchRegCond : public BranchReg 122{ 123 protected: 124 // This will mask the condition code stored for PredOp. Ideally these two 125 // class would cooperate, but they're not set up to do that at the moment. 126 ConditionCode condCode; 127 128 public: 129 BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 130 IntRegIndex _op1, ConditionCode _condCode) : 131 BranchReg(mnem, _machInst, __opClass, _op1), condCode(_condCode) 132 {} 133}; 134 135// Branch to a target computed with two registers 136class BranchRegReg : public PredOp 137{ 138 protected: 139 IntRegIndex op1; 140 IntRegIndex op2; 141 142 public: 143 BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 144 IntRegIndex _op1, IntRegIndex _op2) : 145 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2) 146 {} 147}; 148 149// Branch to a target computed with an immediate and a register 150class BranchImmReg : public PredOp 151{ 152 protected: 153 int32_t imm; 154 IntRegIndex op1; 155 156 public: 157 BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 158 int32_t _imm, IntRegIndex _op1) : 159 PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1) 160 {} 161}; 162 |
163/** 164 * Base class for branches (PC-relative control transfers), 165 * conditional or unconditional. 166 */ 167class Branch : public PCDependentDisassembly 168{ 169 protected: 170 /// target address (signed) Displacement . --- 39 unchanged lines hidden --- |