1/*
| 1/*
|
2 * Copyright (c) 2010 ARM Limited
| 2 * Copyright (c) 2010,2018 ARM Limited
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
43#define __ARCH_ARM_INSTS_BRANCH_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49// Branch to a target computed with an immediate
50class BranchImm : public PredOp
51{
52 protected:
53 int32_t imm;
54
55 public:
56 BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
57 int32_t _imm) :
58 PredOp(mnem, _machInst, __opClass), imm(_imm)
59 {}
60
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
43#define __ARCH_ARM_INSTS_BRANCH_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46
47namespace ArmISA
48{
49// Branch to a target computed with an immediate
50class BranchImm : public PredOp
51{
52 protected:
53 int32_t imm;
54
55 public:
56 BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
57 int32_t _imm) :
58 PredOp(mnem, _machInst, __opClass), imm(_imm)
59 {}
60
|
| 61 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
61};
62
63// Conditionally Branch to a target computed with an immediate
64class BranchImmCond : public BranchImm
65{
66 public:
67 BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
68 int32_t _imm, ConditionCode _condCode) :
69 BranchImm(mnem, _machInst, __opClass, _imm)
70 {
71 // Only update if this isn't part of an IT block
72 if (!machInst.itstateMask)
73 condCode = _condCode;
74 }
75};
76
77// Branch to a target computed with a register
78class BranchReg : public PredOp
79{
80 protected:
81 IntRegIndex op1;
82
83 public:
84 BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
85 IntRegIndex _op1) :
86 PredOp(mnem, _machInst, __opClass), op1(_op1)
87 {}
| 62};
63
64// Conditionally Branch to a target computed with an immediate
65class BranchImmCond : public BranchImm
66{
67 public:
68 BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
69 int32_t _imm, ConditionCode _condCode) :
70 BranchImm(mnem, _machInst, __opClass, _imm)
71 {
72 // Only update if this isn't part of an IT block
73 if (!machInst.itstateMask)
74 condCode = _condCode;
75 }
76};
77
78// Branch to a target computed with a register
79class BranchReg : public PredOp
80{
81 protected:
82 IntRegIndex op1;
83
84 public:
85 BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
86 IntRegIndex _op1) :
87 PredOp(mnem, _machInst, __opClass), op1(_op1)
88 {}
|
| 89
90 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
88};
89
90// Conditionally Branch to a target computed with a register
91class BranchRegCond : public BranchReg
92{
93 public:
94 BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
95 IntRegIndex _op1, ConditionCode _condCode) :
96 BranchReg(mnem, _machInst, __opClass, _op1)
97 {
98 // Only update if this isn't part of an IT block
99 if (!machInst.itstateMask)
100 condCode = _condCode;
101 }
102};
103
104// Branch to a target computed with two registers
105class BranchRegReg : public PredOp
106{
107 protected:
108 IntRegIndex op1;
109 IntRegIndex op2;
110
111 public:
112 BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
113 IntRegIndex _op1, IntRegIndex _op2) :
114 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
115 {}
| 91};
92
93// Conditionally Branch to a target computed with a register
94class BranchRegCond : public BranchReg
95{
96 public:
97 BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
98 IntRegIndex _op1, ConditionCode _condCode) :
99 BranchReg(mnem, _machInst, __opClass, _op1)
100 {
101 // Only update if this isn't part of an IT block
102 if (!machInst.itstateMask)
103 condCode = _condCode;
104 }
105};
106
107// Branch to a target computed with two registers
108class BranchRegReg : public PredOp
109{
110 protected:
111 IntRegIndex op1;
112 IntRegIndex op2;
113
114 public:
115 BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
116 IntRegIndex _op1, IntRegIndex _op2) :
117 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
118 {}
|
| 119
120 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
116};
117
118// Branch to a target computed with an immediate and a register
119class BranchImmReg : public PredOp
120{
121 protected:
122 int32_t imm;
123 IntRegIndex op1;
124
125 public:
126 BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
127 int32_t _imm, IntRegIndex _op1) :
128 PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
129 {}
130};
131
132}
133
134#endif //__ARCH_ARM_INSTS_BRANCH_HH__
| 121};
122
123// Branch to a target computed with an immediate and a register
124class BranchImmReg : public PredOp
125{
126 protected:
127 int32_t imm;
128 IntRegIndex op1;
129
130 public:
131 BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
132 int32_t _imm, IntRegIndex _op1) :
133 PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
134 {}
135};
136
137}
138
139#endif //__ARCH_ARM_INSTS_BRANCH_HH__
|