1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
30#define __ARCH_ARM_INSTS_BRANCH_HH__
31
32#include "arch/arm/insts/pred_inst.hh"
33
34namespace ArmISA
35{
36/**
37 * Base class for instructions whose disassembly is not purely a
38 * function of the machine instruction (i.e., it depends on the
39 * PC). This class overrides the disassemble() method to check
40 * the PC and symbol table values before re-using a cached
41 * disassembly string. This is necessary for branches and jumps,
42 * where the disassembly string includes the target address (which
43 * may depend on the PC and/or symbol table).
44 */
45class PCDependentDisassembly : public PredOp
46{
47 protected:
48 /// Cached program counter from last disassembly
49 mutable Addr cachedPC;
50
51 /// Cached symbol table pointer from last disassembly
52 mutable const SymbolTable *cachedSymtab;
53
54 /// Constructor
| 1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
30#define __ARCH_ARM_INSTS_BRANCH_HH__
31
32#include "arch/arm/insts/pred_inst.hh"
33
34namespace ArmISA
35{
36/**
37 * Base class for instructions whose disassembly is not purely a
38 * function of the machine instruction (i.e., it depends on the
39 * PC). This class overrides the disassemble() method to check
40 * the PC and symbol table values before re-using a cached
41 * disassembly string. This is necessary for branches and jumps,
42 * where the disassembly string includes the target address (which
43 * may depend on the PC and/or symbol table).
44 */
45class PCDependentDisassembly : public PredOp
46{
47 protected:
48 /// Cached program counter from last disassembly
49 mutable Addr cachedPC;
50
51 /// Cached symbol table pointer from last disassembly
52 mutable const SymbolTable *cachedSymtab;
53
54 /// Constructor
|
55 PCDependentDisassembly(const char *mnem, MachInst _machInst,
| 55 PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
|
56 OpClass __opClass)
57 : PredOp(mnem, _machInst, __opClass),
58 cachedPC(0), cachedSymtab(0)
59 {
60 }
61
62 const std::string &
63 disassemble(Addr pc, const SymbolTable *symtab) const;
64};
65
66/**
67 * Base class for branches (PC-relative control transfers),
68 * conditional or unconditional.
69 */
70class Branch : public PCDependentDisassembly
71{
72 protected:
73 /// target address (signed) Displacement .
74 int32_t disp;
75
76 /// Constructor.
| 56 OpClass __opClass)
57 : PredOp(mnem, _machInst, __opClass),
58 cachedPC(0), cachedSymtab(0)
59 {
60 }
61
62 const std::string &
63 disassemble(Addr pc, const SymbolTable *symtab) const;
64};
65
66/**
67 * Base class for branches (PC-relative control transfers),
68 * conditional or unconditional.
69 */
70class Branch : public PCDependentDisassembly
71{
72 protected:
73 /// target address (signed) Displacement .
74 int32_t disp;
75
76 /// Constructor.
|
77 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
| 77 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
|
78 : PCDependentDisassembly(mnem, _machInst, __opClass),
79 disp(machInst.offset << 2)
80 {
81 //If Bit 26 is 1 then Sign Extend
82 if ( (disp & 0x02000000) > 0 ) {
83 disp |= 0xFC000000;
84 }
85 }
86
87 Addr branchTarget(Addr branchPC) const;
88
89 std::string
90 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
91};
92
93/**
94 * Base class for branch and exchange instructions on the ARM
95 */
96class BranchExchange : public PredOp
97{
98 protected:
99 /// Constructor
| 78 : PCDependentDisassembly(mnem, _machInst, __opClass),
79 disp(machInst.offset << 2)
80 {
81 //If Bit 26 is 1 then Sign Extend
82 if ( (disp & 0x02000000) > 0 ) {
83 disp |= 0xFC000000;
84 }
85 }
86
87 Addr branchTarget(Addr branchPC) const;
88
89 std::string
90 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
91};
92
93/**
94 * Base class for branch and exchange instructions on the ARM
95 */
96class BranchExchange : public PredOp
97{
98 protected:
99 /// Constructor
|
100 BranchExchange(const char *mnem, MachInst _machInst,
| 100 BranchExchange(const char *mnem, ExtMachInst _machInst,
|
101 OpClass __opClass)
102 : PredOp(mnem, _machInst, __opClass)
103 {
104 }
105
106 std::string
107 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
108};
109
110
111/**
112 * Base class for jumps (register-indirect control transfers). In
113 * the Arm ISA, these are always unconditional.
114 */
115class Jump : public PCDependentDisassembly
116{
117 protected:
118
119 /// Displacement to target address (signed).
120 int32_t disp;
121
122 uint32_t target;
123
124 public:
125 /// Constructor
| 101 OpClass __opClass)
102 : PredOp(mnem, _machInst, __opClass)
103 {
104 }
105
106 std::string
107 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
108};
109
110
111/**
112 * Base class for jumps (register-indirect control transfers). In
113 * the Arm ISA, these are always unconditional.
114 */
115class Jump : public PCDependentDisassembly
116{
117 protected:
118
119 /// Displacement to target address (signed).
120 int32_t disp;
121
122 uint32_t target;
123
124 public:
125 /// Constructor
|
126 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
| 126 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
|
127 : PCDependentDisassembly(mnem, _machInst, __opClass),
128 disp(machInst.offset << 2)
129 {
130 }
131
132 Addr branchTarget(ThreadContext *tc) const;
133
134 std::string
135 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
136};
137}
138
139#endif //__ARCH_ARM_INSTS_BRANCH_HH__
| 127 : PCDependentDisassembly(mnem, _machInst, __opClass),
128 disp(machInst.offset << 2)
129 {
130 }
131
132 Addr branchTarget(ThreadContext *tc) const;
133
134 std::string
135 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
136};
137}
138
139#endif //__ARCH_ARM_INSTS_BRANCH_HH__
|