vtophys.cc (5566:3440c9ad49b4) | vtophys.cc (5568:d14250d688d2) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 26 unchanged lines hidden (view full) --- 35#include "arch/alpha/ev5.hh" 36#include "arch/alpha/vtophys.hh" 37#include "base/chunk_generator.hh" 38#include "base/trace.hh" 39#include "cpu/thread_context.hh" 40#include "mem/vport.hh" 41 42using namespace std; | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 26 unchanged lines hidden (view full) --- 35#include "arch/alpha/ev5.hh" 36#include "arch/alpha/vtophys.hh" 37#include "base/chunk_generator.hh" 38#include "base/trace.hh" 39#include "cpu/thread_context.hh" 40#include "mem/vport.hh" 41 42using namespace std; |
43using namespace AlphaISA; | |
44 | 43 |
45AlphaISA::PageTableEntry 46AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr) | 44namespace AlphaISA { 45 46PageTableEntry 47kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr) |
47{ 48 Addr level1_pte = ptbr + vaddr.level1(); | 48{ 49 Addr level1_pte = ptbr + vaddr.level1(); |
49 AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte); | 50 PageTableEntry level1 = mem->read |
50 if (!level1.valid()) { 51 DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); 52 return 0; 53 } 54 55 Addr level2_pte = level1.paddr() + vaddr.level2(); | 51 if (!level1.valid()) { 52 DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); 53 return 0; 54 } 55 56 Addr level2_pte = level1.paddr() + vaddr.level2(); |
56 AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte); | 57 PageTableEntry level2 = mem->read |
57 if (!level2.valid()) { 58 DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); 59 return 0; 60 } 61 62 Addr level3_pte = level2.paddr() + vaddr.level3(); | 58 if (!level2.valid()) { 59 DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); 60 return 0; 61 } 62 63 Addr level3_pte = level2.paddr() + vaddr.level3(); |
63 AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte); | 64 PageTableEntry level3 = mem->read |
64 if (!level3.valid()) { 65 DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); 66 return 0; 67 } 68 return level3; 69} 70 71Addr | 65 if (!level3.valid()) { 66 DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); 67 return 0; 68 } 69 return level3; 70} 71 72Addr |
72AlphaISA::vtophys(Addr vaddr) | 73vtophys(Addr vaddr) |
73{ 74 Addr paddr = 0; | 74{ 75 Addr paddr = 0; |
75 if (AlphaISA::IsUSeg(vaddr)) | 76 if (IsUSeg(vaddr)) |
76 DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); | 77 DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); |
77 else if (AlphaISA::IsK0Seg(vaddr)) 78 paddr = AlphaISA::K0Seg2Phys(vaddr); | 78 else if (IsK0Seg(vaddr)) 79 paddr = K0Seg2Phys(vaddr); |
79 else 80 panic("vtophys: ptbr is not set on virtual lookup"); 81 82 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 83 84 return paddr; 85} 86 87Addr | 80 else 81 panic("vtophys: ptbr is not set on virtual lookup"); 82 83 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 84 85 return paddr; 86} 87 88Addr |
88AlphaISA::vtophys(ThreadContext *tc, Addr addr) | 89vtophys(ThreadContext *tc, Addr addr) |
89{ | 90{ |
90 AlphaISA::VAddr vaddr = addr; 91 Addr ptbr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20); | 91 VAddr vaddr = addr; 92 Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20); |
92 Addr paddr = 0; 93 //@todo Andrew couldn't remember why he commented some of this code 94 //so I put it back in. Perhaps something to do with gdb debugging? | 93 Addr paddr = 0; 94 //@todo Andrew couldn't remember why he commented some of this code 95 //so I put it back in. Perhaps something to do with gdb debugging? |
95 if (AlphaISA::PcPAL(vaddr) && (vaddr < AlphaISA::PalMax)) { | 96 if (PcPAL(vaddr) && (vaddr < PalMax)) { |
96 paddr = vaddr & ~ULL(1); 97 } else { | 97 paddr = vaddr & ~ULL(1); 98 } else { |
98 if (AlphaISA::IsK0Seg(vaddr)) { 99 paddr = AlphaISA::K0Seg2Phys(vaddr); | 99 if (IsK0Seg(vaddr)) { 100 paddr = K0Seg2Phys(vaddr); |
100 } else if (!ptbr) { 101 paddr = vaddr; 102 } else { | 101 } else if (!ptbr) { 102 paddr = vaddr; 103 } else { |
103 AlphaISA::PageTableEntry pte = | 104 PageTableEntry pte = |
104 kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); 105 if (pte.valid()) 106 paddr = pte.paddr() | vaddr.offset(); 107 } 108 } 109 110 111 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 112 113 return paddr; 114} 115 | 105 kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); 106 if (pte.valid()) 107 paddr = pte.paddr() | vaddr.offset(); 108 } 109 } 110 111 112 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 113 114 return paddr; 115} 116 |
117} // namespace AlphaISA 118 |
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