1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 * Ali Saidi 31 */ 32 33#include <string> 34 35#include "arch/alpha/ev5.hh" 36#include "arch/alpha/vtophys.hh" 37#include "base/chunk_generator.hh" 38#include "base/trace.hh" 39#include "cpu/thread_context.hh" 40#include "mem/vport.hh" 41 42using namespace std;
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 * Ali Saidi 31 */ 32 33#include <string> 34 35#include "arch/alpha/ev5.hh" 36#include "arch/alpha/vtophys.hh" 37#include "base/chunk_generator.hh" 38#include "base/trace.hh" 39#include "cpu/thread_context.hh" 40#include "mem/vport.hh" 41 42using namespace std;
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43using namespace AlphaISA;
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44
| 43
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45AlphaISA::PageTableEntry 46AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
| 44namespace AlphaISA { 45 46PageTableEntry 47kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr)
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47{ 48 Addr level1_pte = ptbr + vaddr.level1();
| 48{ 49 Addr level1_pte = ptbr + vaddr.level1();
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49 AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
| 50 PageTableEntry level1 = mem->read(level1_pte);
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50 if (!level1.valid()) { 51 DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); 52 return 0; 53 } 54 55 Addr level2_pte = level1.paddr() + vaddr.level2();
| 51 if (!level1.valid()) { 52 DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); 53 return 0; 54 } 55 56 Addr level2_pte = level1.paddr() + vaddr.level2();
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56 AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
| 57 PageTableEntry level2 = mem->read(level2_pte);
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57 if (!level2.valid()) { 58 DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); 59 return 0; 60 } 61 62 Addr level3_pte = level2.paddr() + vaddr.level3();
| 58 if (!level2.valid()) { 59 DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); 60 return 0; 61 } 62 63 Addr level3_pte = level2.paddr() + vaddr.level3();
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63 AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
| 64 PageTableEntry level3 = mem->read(level3_pte);
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64 if (!level3.valid()) { 65 DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); 66 return 0; 67 } 68 return level3; 69} 70 71Addr
| 65 if (!level3.valid()) { 66 DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); 67 return 0; 68 } 69 return level3; 70} 71 72Addr
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72AlphaISA::vtophys(Addr vaddr)
| 73vtophys(Addr vaddr)
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73{ 74 Addr paddr = 0;
| 74{ 75 Addr paddr = 0;
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75 if (AlphaISA::IsUSeg(vaddr))
| 76 if (IsUSeg(vaddr))
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76 DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
| 77 DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
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77 else if (AlphaISA::IsK0Seg(vaddr)) 78 paddr = AlphaISA::K0Seg2Phys(vaddr);
| 78 else if (IsK0Seg(vaddr)) 79 paddr = K0Seg2Phys(vaddr);
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79 else 80 panic("vtophys: ptbr is not set on virtual lookup"); 81 82 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 83 84 return paddr; 85} 86 87Addr
| 80 else 81 panic("vtophys: ptbr is not set on virtual lookup"); 82 83 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 84 85 return paddr; 86} 87 88Addr
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88AlphaISA::vtophys(ThreadContext *tc, Addr addr)
| 89vtophys(ThreadContext *tc, Addr addr)
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89{
| 90{
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90 AlphaISA::VAddr vaddr = addr; 91 Addr ptbr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20);
| 91 VAddr vaddr = addr; 92 Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20);
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92 Addr paddr = 0; 93 //@todo Andrew couldn't remember why he commented some of this code 94 //so I put it back in. Perhaps something to do with gdb debugging?
| 93 Addr paddr = 0; 94 //@todo Andrew couldn't remember why he commented some of this code 95 //so I put it back in. Perhaps something to do with gdb debugging?
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95 if (AlphaISA::PcPAL(vaddr) && (vaddr < AlphaISA::PalMax)) {
| 96 if (PcPAL(vaddr) && (vaddr < PalMax)) {
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96 paddr = vaddr & ~ULL(1); 97 } else {
| 97 paddr = vaddr & ~ULL(1); 98 } else {
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98 if (AlphaISA::IsK0Seg(vaddr)) { 99 paddr = AlphaISA::K0Seg2Phys(vaddr);
| 99 if (IsK0Seg(vaddr)) { 100 paddr = K0Seg2Phys(vaddr);
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100 } else if (!ptbr) { 101 paddr = vaddr; 102 } else {
| 101 } else if (!ptbr) { 102 paddr = vaddr; 103 } else {
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103 AlphaISA::PageTableEntry pte =
| 104 PageTableEntry pte =
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104 kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); 105 if (pte.valid()) 106 paddr = pte.paddr() | vaddr.offset(); 107 } 108 } 109 110 111 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 112 113 return paddr; 114} 115
| 105 kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); 106 if (pte.valid()) 107 paddr = pte.paddr() | vaddr.offset(); 108 } 109 } 110 111 112 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 113 114 return paddr; 115} 116
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| 117} // namespace AlphaISA 118
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