ev5.hh (6025:044903442dcb) ev5.hh (6330:786136379872)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 * Ali Saidi
31 */
32
33#ifndef __ARCH_ALPHA_EV5_HH__
34#define __ARCH_ALPHA_EV5_HH__
35
36#include "arch/alpha/isa_traits.hh"
37
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 * Ali Saidi
31 */
32
33#ifndef __ARCH_ALPHA_EV5_HH__
34#define __ARCH_ALPHA_EV5_HH__
35
36#include "arch/alpha/isa_traits.hh"
37
38class ThreadContext;
39
38namespace AlphaISA {
39
40const uint64_t AsnMask = ULL(0xff);
41const int VAddrImplBits = 43;
42const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
43const Addr VAddrUnImplMask = ~VAddrImplMask;
44inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
45inline Addr VAddrVPN(Addr a) { return a >> PageShift; }

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101const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
102const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
103inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
104inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
105
106const Addr PalBase = 0x4000;
107const Addr PalMax = 0x10000;
108
40namespace AlphaISA {
41
42const uint64_t AsnMask = ULL(0xff);
43const int VAddrImplBits = 43;
44const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
45const Addr VAddrUnImplMask = ~VAddrImplMask;
46inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
47inline Addr VAddrVPN(Addr a) { return a >> PageShift; }

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103const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
104const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
105inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
106inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
107
108const Addr PalBase = 0x4000;
109const Addr PalMax = 0x10000;
110
111void copyIprs(ThreadContext *src, ThreadContext *dest);
112
109} // namespace AlphaISA
110
111#endif // __ARCH_ALPHA_EV5_HH__
113} // namespace AlphaISA
114
115#endif // __ARCH_ALPHA_EV5_HH__