ev5.hh (5570:13592d41f290) ev5.hh (6025:044903442dcb)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Ali Saidi
31 */
32
33#ifndef __ARCH_ALPHA_EV5_HH__
34#define __ARCH_ALPHA_EV5_HH__
35
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 * Ali Saidi
31 */
32
33#ifndef __ARCH_ALPHA_EV5_HH__
34#define __ARCH_ALPHA_EV5_HH__
35
36#include "config/alpha_tlaser.hh"
37#include "arch/alpha/isa_traits.hh"
38
39namespace AlphaISA {
40
36#include "arch/alpha/isa_traits.hh"
37
38namespace AlphaISA {
39
41#if ALPHA_TLASER
42const uint64_t AsnMask = ULL(0x7f);
43#else
44const uint64_t AsnMask = ULL(0xff);
40const uint64_t AsnMask = ULL(0xff);
45#endif
46
47const int VAddrImplBits = 43;
48const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
49const Addr VAddrUnImplMask = ~VAddrImplMask;
50inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
51inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
52inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
53inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
54inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
55
41const int VAddrImplBits = 43;
42const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
43const Addr VAddrUnImplMask = ~VAddrImplMask;
44inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
45inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
46inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
47inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
48inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
49
56#if ALPHA_TLASER
57inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
58const int PAddrImplBits = 40;
59#else
60inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
61const int PAddrImplBits = 44; // for Tsunami
50inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
51const int PAddrImplBits = 44; // for Tsunami
62#endif
63const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
64const Addr PAddrUncachedBit39 = ULL(0x8000000000);
65const Addr PAddrUncachedBit40 = ULL(0x10000000000);
66const Addr PAddrUncachedBit43 = ULL(0x80000000000);
67const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
68
69inline Addr
70Phys2K0Seg(Addr addr)
71{
52const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
53const Addr PAddrUncachedBit39 = ULL(0x8000000000);
54const Addr PAddrUncachedBit40 = ULL(0x10000000000);
55const Addr PAddrUncachedBit43 = ULL(0x80000000000);
56const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
57
58inline Addr
59Phys2K0Seg(Addr addr)
60{
72#if !ALPHA_TLASER
73 if (addr & PAddrUncachedBit43) {
74 addr &= PAddrUncachedMask;
75 addr |= PAddrUncachedBit40;
76 }
61 if (addr & PAddrUncachedBit43) {
62 addr &= PAddrUncachedMask;
63 addr |= PAddrUncachedBit40;
64 }
77#endif
78 return addr | K0SegBase;
79}
80
81inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
82inline Addr DTB_PTE_PPN(uint64_t reg)
83{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
84inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
85inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }

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66}
67
68inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
69inline Addr DTB_PTE_PPN(uint64_t reg)
70{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
71inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
72inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }

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