ev5.hh (5569:baeee670d4ce) ev5.hh (5570:13592d41f290)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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75 addr |= PAddrUncachedBit40;
76 }
77#endif
78 return addr | K0SegBase;
79}
80
81inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
82inline Addr DTB_PTE_PPN(uint64_t reg)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 66 unchanged lines hidden (view full) ---

75 addr |= PAddrUncachedBit40;
76 }
77#endif
78 return addr | K0SegBase;
79}
80
81inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
82inline Addr DTB_PTE_PPN(uint64_t reg)
83{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
83{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
84inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
85inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
86inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
87inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
88inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
89inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
90
91inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
92inline Addr ITB_PTE_PPN(uint64_t reg)
84inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
85inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
86inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
87inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
88inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
89inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
90
91inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
92inline Addr ITB_PTE_PPN(uint64_t reg)
93{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
93{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
94inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
95inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
96inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
97inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
98inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
99
100inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
101

--- 23 unchanged lines hidden --- 		94inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
95inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
96inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
97inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
98inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
99
100inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
101

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