ev5.hh (5566:3440c9ad49b4) ev5.hh (5568:d14250d688d2)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43#else
44const uint64_t AsnMask = ULL(0xff);
45#endif
46
47const int VAddrImplBits = 43;
48const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
49const Addr VAddrUnImplMask = ~VAddrImplMask;
50inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43#else
44const uint64_t AsnMask = ULL(0xff);
45#endif
46
47const int VAddrImplBits = 43;
48const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
49const Addr VAddrUnImplMask = ~VAddrImplMask;
50inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
51inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
52inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
51inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
52inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
53inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
54inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
55
56#if ALPHA_TLASER
57inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
58const int PAddrImplBits = 40;
59#else
60inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }

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68inline Addr Phys2K0Seg(Addr addr)
69{
70#if !ALPHA_TLASER
71 if (addr & PAddrUncachedBit43) {
72 addr &= PAddrUncachedMask;
73 addr |= PAddrUncachedBit40;
74 }
75#endif
53inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
54inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
55
56#if ALPHA_TLASER
57inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
58const int PAddrImplBits = 40;
59#else
60inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }

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68inline Addr Phys2K0Seg(Addr addr)
69{
70#if !ALPHA_TLASER
71 if (addr & PAddrUncachedBit43) {
72 addr &= PAddrUncachedMask;
73 addr |= PAddrUncachedBit40;
74 }
75#endif
76 return addr | AlphaISA::K0SegBase;
76 return addr | K0SegBase;
77}
78
79inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
80inline Addr DTB_PTE_PPN(uint64_t reg)
77}
78
79inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
80inline Addr DTB_PTE_PPN(uint64_t reg)
81{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
81{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
82inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
83inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
84inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
85inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
86inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
87inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
88
89inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
90inline Addr ITB_PTE_PPN(uint64_t reg)
82inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
83inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
84inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
85inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
86inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
87inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
88
89inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
90inline Addr ITB_PTE_PPN(uint64_t reg)
91{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
91{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
92inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
93inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
94inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
95inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
96inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
97
98inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
99

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106inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
107
108const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
109const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
110const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
111const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
112const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
113const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
92inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
93inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
94inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
95inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
96inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
97
98inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
99

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106inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
107
108const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
109const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
110const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
111const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
112const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
113const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
114inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
115inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
114inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
115inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
116
117const Addr PalBase = 0x4000;
118const Addr PalMax = 0x10000;
119
120} // namespace AlphaISA
121
122#endif // __ARCH_ALPHA_EV5_HH__
116
117const Addr PalBase = 0x4000;
118const Addr PalMax = 0x10000;
119
120} // namespace AlphaISA
121
122#endif // __ARCH_ALPHA_EV5_HH__