decoder.h (10152:52c552138ba1) decoder.h (10234:5cb711fa6176)
1/*****************************************************************************
2 * McPAT/CACTI
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
1/*****************************************************************************
2 * McPAT/CACTI
3 * SOFTWARE LICENSE AGREEMENT
4 * Copyright 2012 Hewlett-Packard Development Company, L.P.
5 * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
5 * All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the

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20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
6 * All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the

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21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 ***************************************************************************/
31
32
33#ifndef __DECODER_H__
34#define __DECODER_H__
35
36#include <vector>
37
38#include "area.h"
39#include "component.h"
40#include "parameter.h"
41
42using namespace std;
43
44
30 *
31 ***************************************************************************/
32
33
34#ifndef __DECODER_H__
35#define __DECODER_H__
36
37#include <vector>
38
39#include "area.h"
40#include "component.h"
41#include "parameter.h"
42
43using namespace std;
44
45
45class Decoder : public Component
46{
47 public:
46class Decoder : public Component {
47public:
48 Decoder(
49 int _num_dec_signals,
50 bool flag_way_select,
51 double _C_ld_dec_out,
52 double _R_wire_dec_out,
53 bool fully_assoc_,
54 bool is_dram_,
55 bool is_wl_tr_,

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75 void compute_area();
76 double compute_delays(double inrisetime); // return outrisetime
77
78 void leakage_feedback(double temperature);
79};
80
81
82
48 Decoder(
49 int _num_dec_signals,
50 bool flag_way_select,
51 double _C_ld_dec_out,
52 double _R_wire_dec_out,
53 bool fully_assoc_,
54 bool is_dram_,
55 bool is_wl_tr_,

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75 void compute_area();
76 double compute_delays(double inrisetime); // return outrisetime
77
78 void leakage_feedback(double temperature);
79};
80
81
82
83class PredecBlk : public Component
84{
85 public:
86 PredecBlk(
87 int num_dec_signals,
88 Decoder * dec,
89 double C_wire_predec_blk_out,
90 double R_wire_predec_blk_out,
91 int num_dec_per_predec,
92 bool is_dram_,
93 bool is_blk1);
83class PredecBlk : public Component {
84public:
85 PredecBlk(
86 int num_dec_signals,
87 Decoder * dec,
88 double C_wire_predec_blk_out,
89 double R_wire_predec_blk_out,
90 int num_dec_per_predec,
91 bool is_dram_,
92 bool is_blk1);
94
93
95 Decoder * dec;
96 bool exist;
97 int number_input_addr_bits;
98 double C_ld_predec_blk_out;
99 double R_wire_predec_blk_out;
100 int branch_effort_nand2_gate_output;
101 int branch_effort_nand3_gate_output;
102 bool flag_two_unique_paths;
103 int flag_L2_gate;
104 int number_inputs_L1_gate;
105 int number_gates_L1_nand2_path;
106 int number_gates_L1_nand3_path;
107 int number_gates_L2;
108 int min_number_gates_L1;
109 int min_number_gates_L2;
110 int num_L1_active_nand2_path;
111 int num_L1_active_nand3_path;
112 double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
113 double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
114 double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
115 double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
116 double w_L2_n[MAX_NUMBER_GATES_STAGE];
117 double w_L2_p[MAX_NUMBER_GATES_STAGE];
118 double delay_nand2_path;
119 double delay_nand3_path;
120 powerDef power_nand2_path;
121 powerDef power_nand3_path;
122 powerDef power_L2;
94 Decoder * dec;
95 bool exist;
96 int number_input_addr_bits;
97 double C_ld_predec_blk_out;
98 double R_wire_predec_blk_out;
99 int branch_effort_nand2_gate_output;
100 int branch_effort_nand3_gate_output;
101 bool flag_two_unique_paths;
102 int flag_L2_gate;
103 int number_inputs_L1_gate;
104 int number_gates_L1_nand2_path;
105 int number_gates_L1_nand3_path;
106 int number_gates_L2;
107 int min_number_gates_L1;
108 int min_number_gates_L2;
109 int num_L1_active_nand2_path;
110 int num_L1_active_nand3_path;
111 double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
112 double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
113 double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
114 double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
115 double w_L2_n[MAX_NUMBER_GATES_STAGE];
116 double w_L2_p[MAX_NUMBER_GATES_STAGE];
117 double delay_nand2_path;
118 double delay_nand3_path;
119 powerDef power_nand2_path;
120 powerDef power_nand3_path;
121 powerDef power_L2;
123
122
124 bool is_dram_;
123 bool is_dram_;
125
124
126 void compute_widths();
127 void compute_area();
125 void compute_widths();
126 void compute_area();
128
127
129 void leakage_feedback(double temperature);
128 void leakage_feedback(double temperature);
130
129
131 pair compute_delays(pair inrisetime); //
132 // return
130 pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
131 // return <outrise_nand2, outrise_nand3>
133};
134
135
132};
133
134
136class PredecBlkDrv : public Component
137{
138 public:
139 PredecBlkDrv(
140 int way_select,
141 PredecBlk * blk_,
142 bool is_dram);
135class PredecBlkDrv : public Component {
136public:
137 PredecBlkDrv(
138 int way_select,
139 PredecBlk * blk_,
140 bool is_dram);
143
141
144 int flag_driver_exists;
145 int number_input_addr_bits;
146 int number_gates_nand2_path;
147 int number_gates_nand3_path;
148 int min_number_gates;
149 int num_buffers_driving_1_nand2_load;
150 int num_buffers_driving_2_nand2_load;
151 int num_buffers_driving_4_nand2_load;
152 int num_buffers_driving_2_nand3_load;
153 int num_buffers_driving_8_nand3_load;
154 int num_buffers_nand3_path;
155 double c_load_nand2_path_out;
156 double c_load_nand3_path_out;
157 double r_load_nand2_path_out;
158 double r_load_nand3_path_out;
159 double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
160 double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
161 double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
162 double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
163 double delay_nand2_path;
164 double delay_nand3_path;
165 powerDef power_nand2_path;
166 powerDef power_nand3_path;
142 int flag_driver_exists;
143 int number_input_addr_bits;
144 int number_gates_nand2_path;
145 int number_gates_nand3_path;
146 int min_number_gates;
147 int num_buffers_driving_1_nand2_load;
148 int num_buffers_driving_2_nand2_load;
149 int num_buffers_driving_4_nand2_load;
150 int num_buffers_driving_2_nand3_load;
151 int num_buffers_driving_8_nand3_load;
152 int num_buffers_nand3_path;
153 double c_load_nand2_path_out;
154 double c_load_nand3_path_out;
155 double r_load_nand2_path_out;
156 double r_load_nand3_path_out;
157 double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
158 double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
159 double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
160 double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
161 double delay_nand2_path;
162 double delay_nand3_path;
163 powerDef power_nand2_path;
164 powerDef power_nand3_path;
167
165
168 PredecBlk * blk;
169 Decoder * dec;
170 bool is_dram_;
171 int way_select;
166 PredecBlk * blk;
167 Decoder * dec;
168 bool is_dram_;
169 int way_select;
172
170
173 void compute_widths();
174 void compute_area();
171 void compute_widths();
172 void compute_area();
175
173
176 void leakage_feedback(double temperature);
174 void leakage_feedback(double temperature);
177
178
175
176
179 pair compute_delays(
180 double inrisetime_nand2_path,
181 double inrisetime_nand3_path); // return
177 pair<double, double> compute_delays(
178 double inrisetime_nand2_path,
179 double inrisetime_nand3_path); // return <outrise_nand2, outrise_nand3>
182
180
183 inline int num_addr_bits_nand2_path()
184 {
185 return num_buffers_driving_1_nand2_load +
186 num_buffers_driving_2_nand2_load +
187 num_buffers_driving_4_nand2_load;
188 }
189 inline int num_addr_bits_nand3_path()
190 {
191 return num_buffers_driving_2_nand3_load +
192 num_buffers_driving_8_nand3_load;
193 }
194 double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
181 inline int num_addr_bits_nand2_path() {
182 return num_buffers_driving_1_nand2_load +
183 num_buffers_driving_2_nand2_load +
184 num_buffers_driving_4_nand2_load;
185 }
186 inline int num_addr_bits_nand3_path() {
187 return num_buffers_driving_2_nand3_load +
188 num_buffers_driving_8_nand3_load;
189 }
190 double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
195};
196
197
198
191};
192
193
194
199class Predec : public Component
200{
201 public:
195class Predec : public Component {
196public:
202 Predec(
203 PredecBlkDrv * drv1,
204 PredecBlkDrv * drv2);
205
206 double compute_delays(double inrisetime); // return outrisetime
207
208 void leakage_feedback(double temperature);
209 PredecBlk * blk1;
210 PredecBlk * blk2;
211 PredecBlkDrv * drv1;
212 PredecBlkDrv * drv2;
213
214 powerDef block_power;
215 powerDef driver_power;
216
197 Predec(
198 PredecBlkDrv * drv1,
199 PredecBlkDrv * drv2);
200
201 double compute_delays(double inrisetime); // return outrisetime
202
203 void leakage_feedback(double temperature);
204 PredecBlk * blk1;
205 PredecBlk * blk2;
206 PredecBlkDrv * drv1;
207 PredecBlkDrv * drv2;
208
209 powerDef block_power;
210 powerDef driver_power;
211
217 private:
212private:
218 // returns <delay, risetime>
219 pair<double, double> get_max_delay_before_decoder(
220 pair<double, double> input_pair1,
221 pair<double, double> input_pair2);
222};
223
224
225
213 // returns <delay, risetime>
214 pair<double, double> get_max_delay_before_decoder(
215 pair<double, double> input_pair1,
216 pair<double, double> input_pair2);
217};
218
219
220
226class Driver : public Component
227{
228 public:
229 Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
221class Driver : public Component {
222public:
223 Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
230
224
231 int number_gates;
232 int min_number_gates;
233 double width_n[MAX_NUMBER_GATES_STAGE];
234 double width_p[MAX_NUMBER_GATES_STAGE];
235 double c_gate_load;
236 double c_wire_load;
237 double r_wire_load;
238 double delay;
239 powerDef power;
240 bool is_dram_;
225 int number_gates;
226 int min_number_gates;
227 double width_n[MAX_NUMBER_GATES_STAGE];
228 double width_p[MAX_NUMBER_GATES_STAGE];
229 double c_gate_load;
230 double c_wire_load;
231 double r_wire_load;
232 double delay;
233 powerDef power;
234 bool is_dram_;
241
235
242 void compute_widths();
243 double compute_delay(double inrisetime);
236 void compute_widths();
237 double compute_delay(double inrisetime);
244};
245
246
247#endif
238};
239
240
241#endif