4a5
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45,47c46,47
< class Decoder : public Component
< {
< public:
---
> class Decoder : public Component {
> public:
83,93c83,92
< class PredecBlk : public Component
< {
< public:
< PredecBlk(
< int num_dec_signals,
< Decoder * dec,
< double C_wire_predec_blk_out,
< double R_wire_predec_blk_out,
< int num_dec_per_predec,
< bool is_dram_,
< bool is_blk1);
---
> class PredecBlk : public Component {
> public:
> PredecBlk(
> int num_dec_signals,
> Decoder * dec,
> double C_wire_predec_blk_out,
> double R_wire_predec_blk_out,
> int num_dec_per_predec,
> bool is_dram_,
> bool is_blk1);
95,122c94,121
< Decoder * dec;
< bool exist;
< int number_input_addr_bits;
< double C_ld_predec_blk_out;
< double R_wire_predec_blk_out;
< int branch_effort_nand2_gate_output;
< int branch_effort_nand3_gate_output;
< bool flag_two_unique_paths;
< int flag_L2_gate;
< int number_inputs_L1_gate;
< int number_gates_L1_nand2_path;
< int number_gates_L1_nand3_path;
< int number_gates_L2;
< int min_number_gates_L1;
< int min_number_gates_L2;
< int num_L1_active_nand2_path;
< int num_L1_active_nand3_path;
< double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
< double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
< double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
< double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
< double w_L2_n[MAX_NUMBER_GATES_STAGE];
< double w_L2_p[MAX_NUMBER_GATES_STAGE];
< double delay_nand2_path;
< double delay_nand3_path;
< powerDef power_nand2_path;
< powerDef power_nand3_path;
< powerDef power_L2;
---
> Decoder * dec;
> bool exist;
> int number_input_addr_bits;
> double C_ld_predec_blk_out;
> double R_wire_predec_blk_out;
> int branch_effort_nand2_gate_output;
> int branch_effort_nand3_gate_output;
> bool flag_two_unique_paths;
> int flag_L2_gate;
> int number_inputs_L1_gate;
> int number_gates_L1_nand2_path;
> int number_gates_L1_nand3_path;
> int number_gates_L2;
> int min_number_gates_L1;
> int min_number_gates_L2;
> int num_L1_active_nand2_path;
> int num_L1_active_nand3_path;
> double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
> double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
> double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
> double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
> double w_L2_n[MAX_NUMBER_GATES_STAGE];
> double w_L2_p[MAX_NUMBER_GATES_STAGE];
> double delay_nand2_path;
> double delay_nand3_path;
> powerDef power_nand2_path;
> powerDef power_nand3_path;
> powerDef power_L2;
124c123
< bool is_dram_;
---
> bool is_dram_;
126,127c125,126
< void compute_widths();
< void compute_area();
---
> void compute_widths();
> void compute_area();
129c128
< void leakage_feedback(double temperature);
---
> void leakage_feedback(double temperature);
131,132c130,131
< pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
< // return <outrise_nand2, outrise_nand3>
---
> pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
> // return <outrise_nand2, outrise_nand3>
136,142c135,140
< class PredecBlkDrv : public Component
< {
< public:
< PredecBlkDrv(
< int way_select,
< PredecBlk * blk_,
< bool is_dram);
---
> class PredecBlkDrv : public Component {
> public:
> PredecBlkDrv(
> int way_select,
> PredecBlk * blk_,
> bool is_dram);
144,166c142,164
< int flag_driver_exists;
< int number_input_addr_bits;
< int number_gates_nand2_path;
< int number_gates_nand3_path;
< int min_number_gates;
< int num_buffers_driving_1_nand2_load;
< int num_buffers_driving_2_nand2_load;
< int num_buffers_driving_4_nand2_load;
< int num_buffers_driving_2_nand3_load;
< int num_buffers_driving_8_nand3_load;
< int num_buffers_nand3_path;
< double c_load_nand2_path_out;
< double c_load_nand3_path_out;
< double r_load_nand2_path_out;
< double r_load_nand3_path_out;
< double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
< double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
< double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
< double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
< double delay_nand2_path;
< double delay_nand3_path;
< powerDef power_nand2_path;
< powerDef power_nand3_path;
---
> int flag_driver_exists;
> int number_input_addr_bits;
> int number_gates_nand2_path;
> int number_gates_nand3_path;
> int min_number_gates;
> int num_buffers_driving_1_nand2_load;
> int num_buffers_driving_2_nand2_load;
> int num_buffers_driving_4_nand2_load;
> int num_buffers_driving_2_nand3_load;
> int num_buffers_driving_8_nand3_load;
> int num_buffers_nand3_path;
> double c_load_nand2_path_out;
> double c_load_nand3_path_out;
> double r_load_nand2_path_out;
> double r_load_nand3_path_out;
> double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
> double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
> double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
> double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
> double delay_nand2_path;
> double delay_nand3_path;
> powerDef power_nand2_path;
> powerDef power_nand3_path;
168,171c166,169
< PredecBlk * blk;
< Decoder * dec;
< bool is_dram_;
< int way_select;
---
> PredecBlk * blk;
> Decoder * dec;
> bool is_dram_;
> int way_select;
173,174c171,172
< void compute_widths();
< void compute_area();
---
> void compute_widths();
> void compute_area();
176c174
< void leakage_feedback(double temperature);
---
> void leakage_feedback(double temperature);
179,181c177,179
< pair<double, double> compute_delays(
< double inrisetime_nand2_path,
< double inrisetime_nand3_path); // return <outrise_nand2, outrise_nand3>
---
> pair<double, double> compute_delays(
> double inrisetime_nand2_path,
> double inrisetime_nand3_path); // return <outrise_nand2, outrise_nand3>
183,194c181,190
< inline int num_addr_bits_nand2_path()
< {
< return num_buffers_driving_1_nand2_load +
< num_buffers_driving_2_nand2_load +
< num_buffers_driving_4_nand2_load;
< }
< inline int num_addr_bits_nand3_path()
< {
< return num_buffers_driving_2_nand3_load +
< num_buffers_driving_8_nand3_load;
< }
< double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
---
> inline int num_addr_bits_nand2_path() {
> return num_buffers_driving_1_nand2_load +
> num_buffers_driving_2_nand2_load +
> num_buffers_driving_4_nand2_load;
> }
> inline int num_addr_bits_nand3_path() {
> return num_buffers_driving_2_nand3_load +
> num_buffers_driving_8_nand3_load;
> }
> double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
199,201c195,196
< class Predec : public Component
< {
< public:
---
> class Predec : public Component {
> public:
217c212
< private:
---
> private:
226,229c221,223
< class Driver : public Component
< {
< public:
< Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
---
> class Driver : public Component {
> public:
> Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
231,240c225,234
< int number_gates;
< int min_number_gates;
< double width_n[MAX_NUMBER_GATES_STAGE];
< double width_p[MAX_NUMBER_GATES_STAGE];
< double c_gate_load;
< double c_wire_load;
< double r_wire_load;
< double delay;
< powerDef power;
< bool is_dram_;
---
> int number_gates;
> int min_number_gates;
> double width_n[MAX_NUMBER_GATES_STAGE];
> double width_p[MAX_NUMBER_GATES_STAGE];
> double c_gate_load;
> double c_wire_load;
> double r_wire_load;
> double delay;
> powerDef power;
> bool is_dram_;
242,243c236,237
< void compute_widths();
< double compute_delay(double inrisetime);
---
> void compute_widths();
> double compute_delay(double inrisetime);
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45,47c46,47
< class Decoder : public Component
< {
< public:
---
> class Decoder : public Component {
> public:
83,93c83,92
< class PredecBlk : public Component
< {
< public:
< PredecBlk(
< int num_dec_signals,
< Decoder * dec,
< double C_wire_predec_blk_out,
< double R_wire_predec_blk_out,
< int num_dec_per_predec,
< bool is_dram_,
< bool is_blk1);
---
> class PredecBlk : public Component {
> public:
> PredecBlk(
> int num_dec_signals,
> Decoder * dec,
> double C_wire_predec_blk_out,
> double R_wire_predec_blk_out,
> int num_dec_per_predec,
> bool is_dram_,
> bool is_blk1);
95,122c94,121
< Decoder * dec;
< bool exist;
< int number_input_addr_bits;
< double C_ld_predec_blk_out;
< double R_wire_predec_blk_out;
< int branch_effort_nand2_gate_output;
< int branch_effort_nand3_gate_output;
< bool flag_two_unique_paths;
< int flag_L2_gate;
< int number_inputs_L1_gate;
< int number_gates_L1_nand2_path;
< int number_gates_L1_nand3_path;
< int number_gates_L2;
< int min_number_gates_L1;
< int min_number_gates_L2;
< int num_L1_active_nand2_path;
< int num_L1_active_nand3_path;
< double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
< double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
< double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
< double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
< double w_L2_n[MAX_NUMBER_GATES_STAGE];
< double w_L2_p[MAX_NUMBER_GATES_STAGE];
< double delay_nand2_path;
< double delay_nand3_path;
< powerDef power_nand2_path;
< powerDef power_nand3_path;
< powerDef power_L2;
---
> Decoder * dec;
> bool exist;
> int number_input_addr_bits;
> double C_ld_predec_blk_out;
> double R_wire_predec_blk_out;
> int branch_effort_nand2_gate_output;
> int branch_effort_nand3_gate_output;
> bool flag_two_unique_paths;
> int flag_L2_gate;
> int number_inputs_L1_gate;
> int number_gates_L1_nand2_path;
> int number_gates_L1_nand3_path;
> int number_gates_L2;
> int min_number_gates_L1;
> int min_number_gates_L2;
> int num_L1_active_nand2_path;
> int num_L1_active_nand3_path;
> double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
> double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
> double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
> double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
> double w_L2_n[MAX_NUMBER_GATES_STAGE];
> double w_L2_p[MAX_NUMBER_GATES_STAGE];
> double delay_nand2_path;
> double delay_nand3_path;
> powerDef power_nand2_path;
> powerDef power_nand3_path;
> powerDef power_L2;
124c123
< bool is_dram_;
---
> bool is_dram_;
126,127c125,126
< void compute_widths();
< void compute_area();
---
> void compute_widths();
> void compute_area();
129c128
< void leakage_feedback(double temperature);
---
> void leakage_feedback(double temperature);
131,132c130,131
< pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
< // return <outrise_nand2, outrise_nand3>
---
> pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
> // return <outrise_nand2, outrise_nand3>
136,142c135,140
< class PredecBlkDrv : public Component
< {
< public:
< PredecBlkDrv(
< int way_select,
< PredecBlk * blk_,
< bool is_dram);
---
> class PredecBlkDrv : public Component {
> public:
> PredecBlkDrv(
> int way_select,
> PredecBlk * blk_,
> bool is_dram);
144,166c142,164
< int flag_driver_exists;
< int number_input_addr_bits;
< int number_gates_nand2_path;
< int number_gates_nand3_path;
< int min_number_gates;
< int num_buffers_driving_1_nand2_load;
< int num_buffers_driving_2_nand2_load;
< int num_buffers_driving_4_nand2_load;
< int num_buffers_driving_2_nand3_load;
< int num_buffers_driving_8_nand3_load;
< int num_buffers_nand3_path;
< double c_load_nand2_path_out;
< double c_load_nand3_path_out;
< double r_load_nand2_path_out;
< double r_load_nand3_path_out;
< double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
< double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
< double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
< double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
< double delay_nand2_path;
< double delay_nand3_path;
< powerDef power_nand2_path;
< powerDef power_nand3_path;
---
> int flag_driver_exists;
> int number_input_addr_bits;
> int number_gates_nand2_path;
> int number_gates_nand3_path;
> int min_number_gates;
> int num_buffers_driving_1_nand2_load;
> int num_buffers_driving_2_nand2_load;
> int num_buffers_driving_4_nand2_load;
> int num_buffers_driving_2_nand3_load;
> int num_buffers_driving_8_nand3_load;
> int num_buffers_nand3_path;
> double c_load_nand2_path_out;
> double c_load_nand3_path_out;
> double r_load_nand2_path_out;
> double r_load_nand3_path_out;
> double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
> double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
> double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
> double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
> double delay_nand2_path;
> double delay_nand3_path;
> powerDef power_nand2_path;
> powerDef power_nand3_path;
168,171c166,169
< PredecBlk * blk;
< Decoder * dec;
< bool is_dram_;
< int way_select;
---
> PredecBlk * blk;
> Decoder * dec;
> bool is_dram_;
> int way_select;
173,174c171,172
< void compute_widths();
< void compute_area();
---
> void compute_widths();
> void compute_area();
176c174
< void leakage_feedback(double temperature);
---
> void leakage_feedback(double temperature);
179,181c177,179
< pair<double, double> compute_delays(
< double inrisetime_nand2_path,
< double inrisetime_nand3_path); // return <outrise_nand2, outrise_nand3>
---
> pair<double, double> compute_delays(
> double inrisetime_nand2_path,
> double inrisetime_nand3_path); // return <outrise_nand2, outrise_nand3>
183,194c181,190
< inline int num_addr_bits_nand2_path()
< {
< return num_buffers_driving_1_nand2_load +
< num_buffers_driving_2_nand2_load +
< num_buffers_driving_4_nand2_load;
< }
< inline int num_addr_bits_nand3_path()
< {
< return num_buffers_driving_2_nand3_load +
< num_buffers_driving_8_nand3_load;
< }
< double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
---
> inline int num_addr_bits_nand2_path() {
> return num_buffers_driving_1_nand2_load +
> num_buffers_driving_2_nand2_load +
> num_buffers_driving_4_nand2_load;
> }
> inline int num_addr_bits_nand3_path() {
> return num_buffers_driving_2_nand3_load +
> num_buffers_driving_8_nand3_load;
> }
> double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
199,201c195,196
< class Predec : public Component
< {
< public:
---
> class Predec : public Component {
> public:
217c212
< private:
---
> private:
226,229c221,223
< class Driver : public Component
< {
< public:
< Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
---
> class Driver : public Component {
> public:
> Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
231,240c225,234
< int number_gates;
< int min_number_gates;
< double width_n[MAX_NUMBER_GATES_STAGE];
< double width_p[MAX_NUMBER_GATES_STAGE];
< double c_gate_load;
< double c_wire_load;
< double r_wire_load;
< double delay;
< powerDef power;
< bool is_dram_;
---
> int number_gates;
> int min_number_gates;
> double width_n[MAX_NUMBER_GATES_STAGE];
> double width_p[MAX_NUMBER_GATES_STAGE];
> double c_gate_load;
> double c_wire_load;
> double r_wire_load;
> double delay;
> powerDef power;
> bool is_dram_;
242,243c236,237
< void compute_widths();
< double compute_delay(double inrisetime);
---
> void compute_widths();
> double compute_delay(double inrisetime);