4a5
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48,49c49
< :area(), power(), rt_power(),delay(0)
< {
---
> : area(), power(), rt_power(), delay(0) {
54,55c54
< Component::~Component()
< {
---
> Component::~Component() {
60,66c59,64
< double Component::compute_diffusion_width(int num_stacked_in, int num_folded_tr)
< {
< double w_poly = g_ip->F_sz_um;
< double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
< double total_diff_w = 2 * spacing_poly_to_poly + // for both source and drain
< num_stacked_in * w_poly +
< (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
---
> double Component::compute_diffusion_width(int num_stacked_in, int num_folded_tr) {
> double w_poly = g_ip->F_sz_um;
> double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
> double total_diff_w = 2 * spacing_poly_to_poly + // for both source and drain
> num_stacked_in * w_poly +
> (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
68,73c66,70
< if (num_folded_tr > 1)
< {
< total_diff_w += (num_folded_tr - 2) * 2 * spacing_poly_to_poly +
< (num_folded_tr - 1) * num_stacked_in * w_poly +
< (num_folded_tr - 1) * (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
< }
---
> if (num_folded_tr > 1) {
> total_diff_w += (num_folded_tr - 2) * 2 * spacing_poly_to_poly +
> (num_folded_tr - 1) * num_stacked_in * w_poly +
> (num_folded_tr - 1) * (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
> }
75c72
< return total_diff_w;
---
> return total_diff_w;
85,90c82,85
< double h_gate)
< {
< if (w_pmos <= 0.0 || w_nmos <= 0.0)
< {
< return 0.0;
< }
---
> double h_gate) {
> if (w_pmos <= 0.0 || w_nmos <= 0.0) {
> return 0.0;
> }
92,95c87,90
< double w_folded_pmos, w_folded_nmos;
< int num_folded_pmos, num_folded_nmos;
< double total_ndiff_w, total_pdiff_w;
< Area gate;
---
> double w_folded_pmos, w_folded_nmos;
> int num_folded_pmos, num_folded_nmos;
> double total_ndiff_w, total_pdiff_w;
> Area gate;
97,98c92,93
< double h_tr_region = h_gate - 2 * g_tp.HPOWERRAIL;
< double ratio_p_to_n = w_pmos / (w_pmos + w_nmos);
---
> double h_tr_region = h_gate - 2 * g_tp.HPOWERRAIL;
> double ratio_p_to_n = w_pmos / (w_pmos + w_nmos);
100,103c95,97
< if (ratio_p_to_n >= 1 || ratio_p_to_n <= 0)
< {
< return 0.0;
< }
---
> if (ratio_p_to_n >= 1 || ratio_p_to_n <= 0) {
> return 0.0;
> }
105,107c99,101
< w_folded_pmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * ratio_p_to_n;
< w_folded_nmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * (1 - ratio_p_to_n);
< assert(w_folded_pmos > 0);
---
> w_folded_pmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * ratio_p_to_n;
> w_folded_nmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * (1 - ratio_p_to_n);
> assert(w_folded_pmos > 0);
109,110c103,104
< num_folded_pmos = (int) (ceil(w_pmos / w_folded_pmos));
< num_folded_nmos = (int) (ceil(w_nmos / w_folded_nmos));
---
> num_folded_pmos = (int) (ceil(w_pmos / w_folded_pmos));
> num_folded_nmos = (int) (ceil(w_nmos / w_folded_nmos));
112,113c106
< switch (gate_type)
< {
---
> switch (gate_type) {
115,117c108,110
< total_ndiff_w = compute_diffusion_width(1, num_folded_nmos);
< total_pdiff_w = compute_diffusion_width(1, num_folded_pmos);
< break;
---
> total_ndiff_w = compute_diffusion_width(1, num_folded_nmos);
> total_pdiff_w = compute_diffusion_width(1, num_folded_pmos);
> break;
120,122c113,115
< total_ndiff_w = compute_diffusion_width(1, num_inputs * num_folded_nmos);
< total_pdiff_w = compute_diffusion_width(num_inputs, num_folded_pmos);
< break;
---
> total_ndiff_w = compute_diffusion_width(1, num_inputs * num_folded_nmos);
> total_pdiff_w = compute_diffusion_width(num_inputs, num_folded_pmos);
> break;
125,127c118,120
< total_ndiff_w = compute_diffusion_width(num_inputs, num_folded_nmos);
< total_pdiff_w = compute_diffusion_width(1, num_inputs * num_folded_pmos);
< break;
---
> total_ndiff_w = compute_diffusion_width(num_inputs, num_folded_nmos);
> total_pdiff_w = compute_diffusion_width(1, num_inputs * num_folded_pmos);
> break;
129,131c122,124
< cout << "Unknown gate type: " << gate_type << endl;
< exit(1);
< }
---
> cout << "Unknown gate type: " << gate_type << endl;
> exit(1);
> }
133c126
< gate.w = MAX(total_ndiff_w, total_pdiff_w);
---
> gate.w = MAX(total_ndiff_w, total_pdiff_w);
135,145c128,135
< if (w_folded_nmos > w_nmos)
< {
< //means that the height of the gate can
< //be made smaller than the input height specified, so calculate the height of the gate.
< gate.h = w_nmos + w_pmos + g_tp.MIN_GAP_BET_P_AND_N_DIFFS + 2 * g_tp.HPOWERRAIL;
< }
< else
< {
< gate.h = h_gate;
< }
< return gate.get_area();
---
> if (w_folded_nmos > w_nmos) {
> //means that the height of the gate can
> //be made smaller than the input height specified, so calculate the height of the gate.
> gate.h = w_nmos + w_pmos + g_tp.MIN_GAP_BET_P_AND_N_DIFFS + 2 * g_tp.HPOWERRAIL;
> } else {
> gate.h = h_gate;
> }
> return gate.get_area();
152,158c142,147
< double threshold_folding_width)
< {//This is actually the width of the cell not the width of a device.
< //The width of a cell and the width of a device is orthogonal.
< if (input_width <= 0)
< {
< return 0;
< }
---
> double threshold_folding_width) {
> //This is actually the width of the cell not the width of a device.
> //The width of a cell and the width of a device is orthogonal.
> if (input_width <= 0) {
> return 0;
> }
160,163c149,152
< int num_folded_tr = (int) (ceil(input_width / threshold_folding_width));
< double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
< double width_poly = g_ip->F_sz_um;
< double total_diff_width = num_folded_tr * width_poly + (num_folded_tr + 1) * spacing_poly_to_poly;
---
> int num_folded_tr = (int) (ceil(input_width / threshold_folding_width));
> double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
> double width_poly = g_ip->F_sz_um;
> double total_diff_width = num_folded_tr * width_poly + (num_folded_tr + 1) * spacing_poly_to_poly;
165c154
< return total_diff_width;
---
> return total_diff_width;
170,175c159,163
< double Component::height_sense_amplifier(double pitch_sense_amp)
< {
< // compute the height occupied by all PMOS transistors
< double h_pmos_tr = compute_tr_width_after_folding(g_tp.w_sense_p, pitch_sense_amp) * 2 +
< compute_tr_width_after_folding(g_tp.w_iso, pitch_sense_amp) +
< 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
---
> double Component::height_sense_amplifier(double pitch_sense_amp) {
> // compute the height occupied by all PMOS transistors
> double h_pmos_tr = compute_tr_width_after_folding(g_tp.w_sense_p, pitch_sense_amp) * 2 +
> compute_tr_width_after_folding(g_tp.w_iso, pitch_sense_amp) +
> 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
177,180c165,168
< // compute the height occupied by all NMOS transistors
< double h_nmos_tr = compute_tr_width_after_folding(g_tp.w_sense_n, pitch_sense_amp) * 2 +
< compute_tr_width_after_folding(g_tp.w_sense_en, pitch_sense_amp) +
< 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
---
> // compute the height occupied by all NMOS transistors
> double h_nmos_tr = compute_tr_width_after_folding(g_tp.w_sense_n, pitch_sense_amp) * 2 +
> compute_tr_width_after_folding(g_tp.w_sense_en, pitch_sense_amp) +
> 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
182,183c170,171
< // compute total height by considering gap between the p and n diffusion areas
< return h_pmos_tr + h_nmos_tr + g_tp.MIN_GAP_BET_P_AND_N_DIFFS;
---
> // compute total height by considering gap between the p and n diffusion areas
> return h_pmos_tr + h_nmos_tr + g_tp.MIN_GAP_BET_P_AND_N_DIFFS;
198,200c186,187
< double max_w_nmos)
< {
< int num_gates = (int) (log(F) / log(fopt));
---
> double max_w_nmos) {
> int num_gates = (int) (log(F) / log(fopt));
202,219c189,190
< // check if num_gates is odd. if so, add 1 to make it even
< num_gates+= (num_gates % 2) ? 1 : 0;
< num_gates = MAX(num_gates, num_gates_min);
<
< // recalculate the effective fanout of each stage
< double f = pow(F, 1.0 / num_gates);
< int i = num_gates - 1;
< double C_in = C_load / f;
< w_n[i] = (1.0 / (1.0 + p_to_n_sz_ratio)) * C_in / gate_C(1, 0, is_dram_, false, is_wl_tr_);
< w_n[i] = MAX(w_n[i], g_tp.min_w_nmos_);
< w_p[i] = p_to_n_sz_ratio * w_n[i];
<
< if (w_n[i] > max_w_nmos)
< {
< double C_ld = gate_C((1 + p_to_n_sz_ratio) * max_w_nmos, 0, is_dram_, false, is_wl_tr_);
< F = g * C_ld / gate_C(w_n[0] + w_p[0], 0, is_dram_, false, is_wl_tr_);
< num_gates = (int) (log(F) / log(fopt)) + 1;
< num_gates+= (num_gates % 2) ? 1 : 0;
---
> // check if num_gates is odd. if so, add 1 to make it even
> num_gates += (num_gates % 2) ? 1 : 0;
221,223c192,198
< f = pow(F, 1.0 / (num_gates - 1));
< i = num_gates - 1;
< w_n[i] = max_w_nmos;
---
>
> // recalculate the effective fanout of each stage
> double f = pow(F, 1.0 / num_gates);
> int i = num_gates - 1;
> double C_in = C_load / f;
> w_n[i] = (1.0 / (1.0 + p_to_n_sz_ratio)) * C_in / gate_C(1, 0, is_dram_, false, is_wl_tr_);
> w_n[i] = MAX(w_n[i], g_tp.min_w_nmos_);
225d199
< }
227,231c201,211
< for (i = num_gates - 2; i >= 1; i--)
< {
< w_n[i] = MAX(w_n[i+1] / f, g_tp.min_w_nmos_);
< w_p[i] = p_to_n_sz_ratio * w_n[i];
< }
---
> if (w_n[i] > max_w_nmos) {
> double C_ld = gate_C((1 + p_to_n_sz_ratio) * max_w_nmos, 0, is_dram_, false, is_wl_tr_);
> F = g * C_ld / gate_C(w_n[0] + w_p[0], 0, is_dram_, false, is_wl_tr_);
> num_gates = (int) (log(F) / log(fopt)) + 1;
> num_gates += (num_gates % 2) ? 1 : 0;
> num_gates = MAX(num_gates, num_gates_min);
> f = pow(F, 1.0 / (num_gates - 1));
> i = num_gates - 1;
> w_n[i] = max_w_nmos;
> w_p[i] = p_to_n_sz_ratio * w_n[i];
> }
233,234c213,219
< assert(num_gates <= MAX_NUMBER_GATES_STAGE);
< return num_gates;
---
> for (i = num_gates - 2; i >= 1; i--) {
> w_n[i] = MAX(w_n[i+1] / f, g_tp.min_w_nmos_);
> w_p[i] = p_to_n_sz_ratio * w_n[i];
> }
>
> assert(num_gates <= MAX_NUMBER_GATES_STAGE);
> return num_gates;
> * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
28c29
< * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
---
> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48,49c49
< :area(), power(), rt_power(),delay(0)
< {
---
> : area(), power(), rt_power(), delay(0) {
54,55c54
< Component::~Component()
< {
---
> Component::~Component() {
60,66c59,64
< double Component::compute_diffusion_width(int num_stacked_in, int num_folded_tr)
< {
< double w_poly = g_ip->F_sz_um;
< double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
< double total_diff_w = 2 * spacing_poly_to_poly + // for both source and drain
< num_stacked_in * w_poly +
< (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
---
> double Component::compute_diffusion_width(int num_stacked_in, int num_folded_tr) {
> double w_poly = g_ip->F_sz_um;
> double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
> double total_diff_w = 2 * spacing_poly_to_poly + // for both source and drain
> num_stacked_in * w_poly +
> (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
68,73c66,70
< if (num_folded_tr > 1)
< {
< total_diff_w += (num_folded_tr - 2) * 2 * spacing_poly_to_poly +
< (num_folded_tr - 1) * num_stacked_in * w_poly +
< (num_folded_tr - 1) * (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
< }
---
> if (num_folded_tr > 1) {
> total_diff_w += (num_folded_tr - 2) * 2 * spacing_poly_to_poly +
> (num_folded_tr - 1) * num_stacked_in * w_poly +
> (num_folded_tr - 1) * (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
> }
75c72
< return total_diff_w;
---
> return total_diff_w;
85,90c82,85
< double h_gate)
< {
< if (w_pmos <= 0.0 || w_nmos <= 0.0)
< {
< return 0.0;
< }
---
> double h_gate) {
> if (w_pmos <= 0.0 || w_nmos <= 0.0) {
> return 0.0;
> }
92,95c87,90
< double w_folded_pmos, w_folded_nmos;
< int num_folded_pmos, num_folded_nmos;
< double total_ndiff_w, total_pdiff_w;
< Area gate;
---
> double w_folded_pmos, w_folded_nmos;
> int num_folded_pmos, num_folded_nmos;
> double total_ndiff_w, total_pdiff_w;
> Area gate;
97,98c92,93
< double h_tr_region = h_gate - 2 * g_tp.HPOWERRAIL;
< double ratio_p_to_n = w_pmos / (w_pmos + w_nmos);
---
> double h_tr_region = h_gate - 2 * g_tp.HPOWERRAIL;
> double ratio_p_to_n = w_pmos / (w_pmos + w_nmos);
100,103c95,97
< if (ratio_p_to_n >= 1 || ratio_p_to_n <= 0)
< {
< return 0.0;
< }
---
> if (ratio_p_to_n >= 1 || ratio_p_to_n <= 0) {
> return 0.0;
> }
105,107c99,101
< w_folded_pmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * ratio_p_to_n;
< w_folded_nmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * (1 - ratio_p_to_n);
< assert(w_folded_pmos > 0);
---
> w_folded_pmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * ratio_p_to_n;
> w_folded_nmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * (1 - ratio_p_to_n);
> assert(w_folded_pmos > 0);
109,110c103,104
< num_folded_pmos = (int) (ceil(w_pmos / w_folded_pmos));
< num_folded_nmos = (int) (ceil(w_nmos / w_folded_nmos));
---
> num_folded_pmos = (int) (ceil(w_pmos / w_folded_pmos));
> num_folded_nmos = (int) (ceil(w_nmos / w_folded_nmos));
112,113c106
< switch (gate_type)
< {
---
> switch (gate_type) {
115,117c108,110
< total_ndiff_w = compute_diffusion_width(1, num_folded_nmos);
< total_pdiff_w = compute_diffusion_width(1, num_folded_pmos);
< break;
---
> total_ndiff_w = compute_diffusion_width(1, num_folded_nmos);
> total_pdiff_w = compute_diffusion_width(1, num_folded_pmos);
> break;
120,122c113,115
< total_ndiff_w = compute_diffusion_width(1, num_inputs * num_folded_nmos);
< total_pdiff_w = compute_diffusion_width(num_inputs, num_folded_pmos);
< break;
---
> total_ndiff_w = compute_diffusion_width(1, num_inputs * num_folded_nmos);
> total_pdiff_w = compute_diffusion_width(num_inputs, num_folded_pmos);
> break;
125,127c118,120
< total_ndiff_w = compute_diffusion_width(num_inputs, num_folded_nmos);
< total_pdiff_w = compute_diffusion_width(1, num_inputs * num_folded_pmos);
< break;
---
> total_ndiff_w = compute_diffusion_width(num_inputs, num_folded_nmos);
> total_pdiff_w = compute_diffusion_width(1, num_inputs * num_folded_pmos);
> break;
129,131c122,124
< cout << "Unknown gate type: " << gate_type << endl;
< exit(1);
< }
---
> cout << "Unknown gate type: " << gate_type << endl;
> exit(1);
> }
133c126
< gate.w = MAX(total_ndiff_w, total_pdiff_w);
---
> gate.w = MAX(total_ndiff_w, total_pdiff_w);
135,145c128,135
< if (w_folded_nmos > w_nmos)
< {
< //means that the height of the gate can
< //be made smaller than the input height specified, so calculate the height of the gate.
< gate.h = w_nmos + w_pmos + g_tp.MIN_GAP_BET_P_AND_N_DIFFS + 2 * g_tp.HPOWERRAIL;
< }
< else
< {
< gate.h = h_gate;
< }
< return gate.get_area();
---
> if (w_folded_nmos > w_nmos) {
> //means that the height of the gate can
> //be made smaller than the input height specified, so calculate the height of the gate.
> gate.h = w_nmos + w_pmos + g_tp.MIN_GAP_BET_P_AND_N_DIFFS + 2 * g_tp.HPOWERRAIL;
> } else {
> gate.h = h_gate;
> }
> return gate.get_area();
152,158c142,147
< double threshold_folding_width)
< {//This is actually the width of the cell not the width of a device.
< //The width of a cell and the width of a device is orthogonal.
< if (input_width <= 0)
< {
< return 0;
< }
---
> double threshold_folding_width) {
> //This is actually the width of the cell not the width of a device.
> //The width of a cell and the width of a device is orthogonal.
> if (input_width <= 0) {
> return 0;
> }
160,163c149,152
< int num_folded_tr = (int) (ceil(input_width / threshold_folding_width));
< double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
< double width_poly = g_ip->F_sz_um;
< double total_diff_width = num_folded_tr * width_poly + (num_folded_tr + 1) * spacing_poly_to_poly;
---
> int num_folded_tr = (int) (ceil(input_width / threshold_folding_width));
> double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
> double width_poly = g_ip->F_sz_um;
> double total_diff_width = num_folded_tr * width_poly + (num_folded_tr + 1) * spacing_poly_to_poly;
165c154
< return total_diff_width;
---
> return total_diff_width;
170,175c159,163
< double Component::height_sense_amplifier(double pitch_sense_amp)
< {
< // compute the height occupied by all PMOS transistors
< double h_pmos_tr = compute_tr_width_after_folding(g_tp.w_sense_p, pitch_sense_amp) * 2 +
< compute_tr_width_after_folding(g_tp.w_iso, pitch_sense_amp) +
< 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
---
> double Component::height_sense_amplifier(double pitch_sense_amp) {
> // compute the height occupied by all PMOS transistors
> double h_pmos_tr = compute_tr_width_after_folding(g_tp.w_sense_p, pitch_sense_amp) * 2 +
> compute_tr_width_after_folding(g_tp.w_iso, pitch_sense_amp) +
> 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
177,180c165,168
< // compute the height occupied by all NMOS transistors
< double h_nmos_tr = compute_tr_width_after_folding(g_tp.w_sense_n, pitch_sense_amp) * 2 +
< compute_tr_width_after_folding(g_tp.w_sense_en, pitch_sense_amp) +
< 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
---
> // compute the height occupied by all NMOS transistors
> double h_nmos_tr = compute_tr_width_after_folding(g_tp.w_sense_n, pitch_sense_amp) * 2 +
> compute_tr_width_after_folding(g_tp.w_sense_en, pitch_sense_amp) +
> 2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
182,183c170,171
< // compute total height by considering gap between the p and n diffusion areas
< return h_pmos_tr + h_nmos_tr + g_tp.MIN_GAP_BET_P_AND_N_DIFFS;
---
> // compute total height by considering gap between the p and n diffusion areas
> return h_pmos_tr + h_nmos_tr + g_tp.MIN_GAP_BET_P_AND_N_DIFFS;
198,200c186,187
< double max_w_nmos)
< {
< int num_gates = (int) (log(F) / log(fopt));
---
> double max_w_nmos) {
> int num_gates = (int) (log(F) / log(fopt));
202,219c189,190
< // check if num_gates is odd. if so, add 1 to make it even
< num_gates+= (num_gates % 2) ? 1 : 0;
< num_gates = MAX(num_gates, num_gates_min);
<
< // recalculate the effective fanout of each stage
< double f = pow(F, 1.0 / num_gates);
< int i = num_gates - 1;
< double C_in = C_load / f;
< w_n[i] = (1.0 / (1.0 + p_to_n_sz_ratio)) * C_in / gate_C(1, 0, is_dram_, false, is_wl_tr_);
< w_n[i] = MAX(w_n[i], g_tp.min_w_nmos_);
< w_p[i] = p_to_n_sz_ratio * w_n[i];
<
< if (w_n[i] > max_w_nmos)
< {
< double C_ld = gate_C((1 + p_to_n_sz_ratio) * max_w_nmos, 0, is_dram_, false, is_wl_tr_);
< F = g * C_ld / gate_C(w_n[0] + w_p[0], 0, is_dram_, false, is_wl_tr_);
< num_gates = (int) (log(F) / log(fopt)) + 1;
< num_gates+= (num_gates % 2) ? 1 : 0;
---
> // check if num_gates is odd. if so, add 1 to make it even
> num_gates += (num_gates % 2) ? 1 : 0;
221,223c192,198
< f = pow(F, 1.0 / (num_gates - 1));
< i = num_gates - 1;
< w_n[i] = max_w_nmos;
---
>
> // recalculate the effective fanout of each stage
> double f = pow(F, 1.0 / num_gates);
> int i = num_gates - 1;
> double C_in = C_load / f;
> w_n[i] = (1.0 / (1.0 + p_to_n_sz_ratio)) * C_in / gate_C(1, 0, is_dram_, false, is_wl_tr_);
> w_n[i] = MAX(w_n[i], g_tp.min_w_nmos_);
225d199
< }
227,231c201,211
< for (i = num_gates - 2; i >= 1; i--)
< {
< w_n[i] = MAX(w_n[i+1] / f, g_tp.min_w_nmos_);
< w_p[i] = p_to_n_sz_ratio * w_n[i];
< }
---
> if (w_n[i] > max_w_nmos) {
> double C_ld = gate_C((1 + p_to_n_sz_ratio) * max_w_nmos, 0, is_dram_, false, is_wl_tr_);
> F = g * C_ld / gate_C(w_n[0] + w_p[0], 0, is_dram_, false, is_wl_tr_);
> num_gates = (int) (log(F) / log(fopt)) + 1;
> num_gates += (num_gates % 2) ? 1 : 0;
> num_gates = MAX(num_gates, num_gates_min);
> f = pow(F, 1.0 / (num_gates - 1));
> i = num_gates - 1;
> w_n[i] = max_w_nmos;
> w_p[i] = p_to_n_sz_ratio * w_n[i];
> }
233,234c213,219
< assert(num_gates <= MAX_NUMBER_GATES_STAGE);
< return num_gates;
---
> for (i = num_gates - 2; i >= 1; i--) {
> w_n[i] = MAX(w_n[i+1] / f, g_tp.min_w_nmos_);
> w_p[i] = p_to_n_sz_ratio * w_n[i];
> }
>
> assert(num_gates <= MAX_NUMBER_GATES_STAGE);
> return num_gates;