1# WARNING: Most commercial fabs will not be happy if you release their exact
2# process information! If you derive these numbers through SPICE models,
3# the process design kit, or any other confidential material, please round-off
4# the values and leave the process name unidentifiable by fab (i.e. call it
5# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
6# rule may not apply for open processes, but you may want to check.
7
8# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
9
10# This file contains the model for a bulk 32nm LVT process
11Name = Bulk32LVT
12
13# Supply voltage used in the circuit and for characterizations (V)
14Vdd = 0.9
15# Temperature (K)
16Temperature = 340
17
18# =============================================================================
19# Parameters for transistors
20# =============================================================================
21
22# Contacted gate pitch (m)
23Gate->PitchContacted = 0.160e-6
24
25# Min gate width (m)
26Gate->MinWidth = 0.120e-6
27
28# Gate cap per unit width (F/m)
29Gate->CapPerWidth = 0.950e-9
30# Source/Drain cap per unit width (F/m)
31Drain->CapPerWidth = 0.640e-9
32
33# Parameters characterization temperature (K)
34Nmos->CharacterizedTemperature = 300.0
35Pmos->CharacterizedTemperature = 300.0
36
37#------------------------------------------------------------------------------
38# I_Eff definition in Na, IEDM 2002
39# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
40# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
41# This is generally accurate for when input and output transition times
42# are similar, which is a reasonable case after timing optimization
43#------------------------------------------------------------------------------
44# Effective resistance (Ohm-m)
45Nmos->EffResWidth = 0.890e-3
46Pmos->EffResWidth = 1.270e-3
47
48#------------------------------------------------------------------------------
49# The ratio of extra effective resistance with each additional stacked
50# transistor
51# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
52# For example, inverter has an normalized effective drive resistance of 1.0.
53# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
54# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
55# works relatively well up to 4 stacks. This value will change depending on the
56# VDD used.
57#------------------------------------------------------------------------------
58# Effective resistance stack ratio
59Nmos->EffResStackRatio = 0.78
60Pmos->EffResStackRatio = 0.66
61
62#------------------------------------------------------------------------------
63# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
64# Minimum off current is used as a second fit point, since I_OFF often
65# stops scaling with transistor width below some threshold
66#------------------------------------------------------------------------------
67# Off current per width (A/m)
68Nmos->OffCurrent = 100e-3
69Pmos->OffCurrent = 100e-3
70
71# Minimum off current (A)
72Nmos->MinOffCurrent = 100e-9
73Pmos->MinOffCurrent = 20e-9
74
75# Subthreshold swing (V/dec)
76Nmos->SubthresholdSwing = 0.100
77Pmos->SubthresholdSwing = 0.100
78
79# DIBL factor (V/V)
80Nmos->DIBL = 0.150
81Pmos->DIBL = 0.150
82
83# Subthreshold leakage temperature swing (K/dec)
84Nmos->SubthresholdTempSwing = 100
85Pmos->SubthresholdTempSwing = 100
86#------------------------------------------------------------------------------
87
88# =============================================================================
89# Parameters for interconnect
90# =============================================================================
91
92Wire->AvailableLayers = [Metal1,Local,Intermediate,Global]
93
94# Metal 1 Wire (used for std cell routing only)
95# Min width (m)
96Wire->Metal1->MinWidth = 55e-9
97# Min spacing (m)
98Wire->Metal1->MinSpacing = 55e-9
99# Resistivity (Ohm-m)
100Wire->Metal1->Resistivity = 4.00e-8
101# Metal thickness (m)
102Wire->Metal1->MetalThickness = 100.0e-9
103# Dielectric thickness (m)
104Wire->Metal1->DielectricThickness = 100.0e-9
105# Dielectric constant
106Wire->Metal1->DielectricConstant = 3.2
107
108# Local wire, 1.0X of the M1 pitch
109# Min width (m)
110Wire->Local->MinWidth = 55e-9
111# Min spacing (m)
112Wire->Local->MinSpacing = 55e-9
113# Resistivity (Ohm-m)
114Wire->Local->Resistivity = 4.00e-8
115# Metal thickness (m)
116Wire->Local->MetalThickness = 100.0e-9
117# Dielectric thickness (m)
118Wire->Local->DielectricThickness = 100.0e-9
119# Dielectric constant
120Wire->Local->DielectricConstant = 3.2
121
122# Intermediate wire, 2.0X the M1 pitch
123# Min width (m)
124Wire->Intermediate->MinWidth = 110e-9
125# Min spacing (m)
126Wire->Intermediate->MinSpacing = 110e-9
127# Resistivity (Ohm-m)
128Wire->Intermediate->Resistivity = 2.60e-8
129# Metal thickness (m)
130Wire->Intermediate->MetalThickness = 200e-9
131# Dielectric thickness (m)
132Wire->Intermediate->DielectricThickness = 170e-9
133# Dielectric constant
134Wire->Intermediate->DielectricConstant = 3.00
135
136# Global wire, 3.0X the M1 pitch
137# Min width (m)
138Wire->Global->MinWidth = 160e-9
139# Min spacing (m)
140Wire->Global->MinSpacing = 160e-9
141# Resistivity (Ohm-m)
142Wire->Global->Resistivity = 2.30e-8
143# Metal thickness (m)
144Wire->Global->MetalThickness = 280e-9
145# Dielectric thickness (m)
146Wire->Global->DielectricThickness = 250e-9
147# Dielectric constant
148Wire->Global->DielectricConstant = 2.80
149
150# =============================================================================
151# Parameters for Standard Cells
152# =============================================================================
153
154# The height of the standard cell is usually a multiple of the vertical
155# M1 pitch (tracks). By definition, an X1 size cell has transistors
156# that fit exactly in the given cell height without folding, or leaving
157# any wasted vertical area
158
159# Reasonable values for the number of M1 tracks that we have seen are 8-14
160StdCell->Tracks = 11
161# Height overhead due to supply rails, well spacing, etc. Note that this will grow
162# if the height of the standard cell decreases!
163StdCell->HeightOverheadFactor = 1.400
164
165# Sets the available sizes of each standard cell. Keep in mind that
166# 1.0 is the biggest cell without any transistor folding
167StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
168
2# process information! If you derive these numbers through SPICE models,
3# the process design kit, or any other confidential material, please round-off
4# the values and leave the process name unidentifiable by fab (i.e. call it
5# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
6# rule may not apply for open processes, but you may want to check.
7
8# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
9
10# This file contains the model for a bulk 32nm LVT process
11Name = Bulk32LVT
12
13# Supply voltage used in the circuit and for characterizations (V)
14Vdd = 0.9
15# Temperature (K)
16Temperature = 340
17
18# =============================================================================
19# Parameters for transistors
20# =============================================================================
21
22# Contacted gate pitch (m)
23Gate->PitchContacted = 0.160e-6
24
25# Min gate width (m)
26Gate->MinWidth = 0.120e-6
27
28# Gate cap per unit width (F/m)
29Gate->CapPerWidth = 0.950e-9
30# Source/Drain cap per unit width (F/m)
31Drain->CapPerWidth = 0.640e-9
32
33# Parameters characterization temperature (K)
34Nmos->CharacterizedTemperature = 300.0
35Pmos->CharacterizedTemperature = 300.0
36
37#------------------------------------------------------------------------------
38# I_Eff definition in Na, IEDM 2002
39# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
40# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
41# This is generally accurate for when input and output transition times
42# are similar, which is a reasonable case after timing optimization
43#------------------------------------------------------------------------------
44# Effective resistance (Ohm-m)
45Nmos->EffResWidth = 0.890e-3
46Pmos->EffResWidth = 1.270e-3
47
48#------------------------------------------------------------------------------
49# The ratio of extra effective resistance with each additional stacked
50# transistor
51# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
52# For example, inverter has an normalized effective drive resistance of 1.0.
53# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
54# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
55# works relatively well up to 4 stacks. This value will change depending on the
56# VDD used.
57#------------------------------------------------------------------------------
58# Effective resistance stack ratio
59Nmos->EffResStackRatio = 0.78
60Pmos->EffResStackRatio = 0.66
61
62#------------------------------------------------------------------------------
63# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
64# Minimum off current is used as a second fit point, since I_OFF often
65# stops scaling with transistor width below some threshold
66#------------------------------------------------------------------------------
67# Off current per width (A/m)
68Nmos->OffCurrent = 100e-3
69Pmos->OffCurrent = 100e-3
70
71# Minimum off current (A)
72Nmos->MinOffCurrent = 100e-9
73Pmos->MinOffCurrent = 20e-9
74
75# Subthreshold swing (V/dec)
76Nmos->SubthresholdSwing = 0.100
77Pmos->SubthresholdSwing = 0.100
78
79# DIBL factor (V/V)
80Nmos->DIBL = 0.150
81Pmos->DIBL = 0.150
82
83# Subthreshold leakage temperature swing (K/dec)
84Nmos->SubthresholdTempSwing = 100
85Pmos->SubthresholdTempSwing = 100
86#------------------------------------------------------------------------------
87
88# =============================================================================
89# Parameters for interconnect
90# =============================================================================
91
92Wire->AvailableLayers = [Metal1,Local,Intermediate,Global]
93
94# Metal 1 Wire (used for std cell routing only)
95# Min width (m)
96Wire->Metal1->MinWidth = 55e-9
97# Min spacing (m)
98Wire->Metal1->MinSpacing = 55e-9
99# Resistivity (Ohm-m)
100Wire->Metal1->Resistivity = 4.00e-8
101# Metal thickness (m)
102Wire->Metal1->MetalThickness = 100.0e-9
103# Dielectric thickness (m)
104Wire->Metal1->DielectricThickness = 100.0e-9
105# Dielectric constant
106Wire->Metal1->DielectricConstant = 3.2
107
108# Local wire, 1.0X of the M1 pitch
109# Min width (m)
110Wire->Local->MinWidth = 55e-9
111# Min spacing (m)
112Wire->Local->MinSpacing = 55e-9
113# Resistivity (Ohm-m)
114Wire->Local->Resistivity = 4.00e-8
115# Metal thickness (m)
116Wire->Local->MetalThickness = 100.0e-9
117# Dielectric thickness (m)
118Wire->Local->DielectricThickness = 100.0e-9
119# Dielectric constant
120Wire->Local->DielectricConstant = 3.2
121
122# Intermediate wire, 2.0X the M1 pitch
123# Min width (m)
124Wire->Intermediate->MinWidth = 110e-9
125# Min spacing (m)
126Wire->Intermediate->MinSpacing = 110e-9
127# Resistivity (Ohm-m)
128Wire->Intermediate->Resistivity = 2.60e-8
129# Metal thickness (m)
130Wire->Intermediate->MetalThickness = 200e-9
131# Dielectric thickness (m)
132Wire->Intermediate->DielectricThickness = 170e-9
133# Dielectric constant
134Wire->Intermediate->DielectricConstant = 3.00
135
136# Global wire, 3.0X the M1 pitch
137# Min width (m)
138Wire->Global->MinWidth = 160e-9
139# Min spacing (m)
140Wire->Global->MinSpacing = 160e-9
141# Resistivity (Ohm-m)
142Wire->Global->Resistivity = 2.30e-8
143# Metal thickness (m)
144Wire->Global->MetalThickness = 280e-9
145# Dielectric thickness (m)
146Wire->Global->DielectricThickness = 250e-9
147# Dielectric constant
148Wire->Global->DielectricConstant = 2.80
149
150# =============================================================================
151# Parameters for Standard Cells
152# =============================================================================
153
154# The height of the standard cell is usually a multiple of the vertical
155# M1 pitch (tracks). By definition, an X1 size cell has transistors
156# that fit exactly in the given cell height without folding, or leaving
157# any wasted vertical area
158
159# Reasonable values for the number of M1 tracks that we have seen are 8-14
160StdCell->Tracks = 11
161# Height overhead due to supply rails, well spacing, etc. Note that this will grow
162# if the height of the standard cell decreases!
163StdCell->HeightOverheadFactor = 1.400
164
165# Sets the available sizes of each standard cell. Keep in mind that
166# 1.0 is the biggest cell without any transistor folding
167StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
168