two_level.py (11104:2d537040a4b9) two_level.py (11154:fce93f1c885b)
1# -*- coding: utf-8 -*-
2# Copyright (c) 2015 Jason Power
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 106 unchanged lines hidden (view full) ---

115system.l2cache.connectMemSideBus(system.membus)
116
117# create the interrupt controller for the CPU
118system.cpu.createInterruptController()
119
120# For x86 only, make sure the interrupts are connected to the memory
121# Note: these are directly connected to the memory bus and are not cached
122if m5.defines.buildEnv['TARGET_ISA'] == "x86":
1# -*- coding: utf-8 -*-
2# Copyright (c) 2015 Jason Power
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 106 unchanged lines hidden (view full) ---

115system.l2cache.connectMemSideBus(system.membus)
116
117# create the interrupt controller for the CPU
118system.cpu.createInterruptController()
119
120# For x86 only, make sure the interrupts are connected to the memory
121# Note: these are directly connected to the memory bus and are not cached
122if m5.defines.buildEnv['TARGET_ISA'] == "x86":
123 system.cpu.interrupts.pio = system.membus.master
124 system.cpu.interrupts.int_master = system.membus.slave
125 system.cpu.interrupts.int_slave = system.membus.master
123 system.cpu.interrupts[0].pio = system.membus.master
124 system.cpu.interrupts[0].int_master = system.membus.slave
125 system.cpu.interrupts[0].int_slave = system.membus.master
126
127# Connect the system up to the membus
128system.system_port = system.membus.slave
129
130# Create a DDR3 memory controller
131system.mem_ctrl = DDR3_1600_x64()
132system.mem_ctrl.range = system.mem_ranges[0]
133system.mem_ctrl.port = system.membus.master

--- 18 unchanged lines hidden --- 		126
127# Connect the system up to the membus
128system.system_port = system.membus.slave
129
130# Create a DDR3 memory controller
131system.mem_ctrl = DDR3_1600_x64()
132system.mem_ctrl.range = system.mem_ranges[0]
133system.mem_ctrl.port = system.membus.master

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