| memtest.py (8931:7a1dfb191e3f) | memtest.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 134 unchanged lines hidden (view full) --- 143system = System(funcmem = SimpleMemory(in_addr_map = False), 144 physmem = SimpleMemory(latency = "100ns")) 145 146def make_level(spec, prototypes, attach_obj, attach_port): 147 fanout = spec[0] 148 parent = attach_obj # use attach obj as config parent too 149 if len(spec) > 1 and (fanout > 1 or options.force_bus): 150 port = getattr(attach_obj, attach_port) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 134 unchanged lines hidden (view full) --- 143system = System(funcmem = SimpleMemory(in_addr_map = False), 144 physmem = SimpleMemory(latency = "100ns")) 145 146def make_level(spec, prototypes, attach_obj, attach_port): 147 fanout = spec[0] 148 parent = attach_obj # use attach obj as config parent too 149 if len(spec) > 1 and (fanout > 1 or options.force_bus): 150 port = getattr(attach_obj, attach_port) |
| 151 new_bus = Bus(clock="500MHz", width=16) | 151 new_bus = CoherentBus(clock="500MHz", width=16) |
| 152 if (port.role == 'MASTER'): 153 new_bus.slave = port 154 attach_port = "master" 155 else: 156 new_bus.master = port 157 attach_port = "slave" 158 parent.cpu_side_bus = new_bus 159 attach_obj = new_bus --- 40 unchanged lines hidden --- | 152 if (port.role == 'MASTER'): 153 new_bus.slave = port 154 attach_port = "master" 155 else: 156 new_bus.master = port 157 attach_port = "slave" 158 parent.cpu_side_bus = new_bus 159 attach_obj = new_bus --- 40 unchanged lines hidden --- |