memtest.py (4549:42b30b2529e1) memtest.py (4626:ed8aacb19c03)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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28
29import m5
30from m5.objects import *
31import os, optparse, sys
32m5.AddToPath('../common')
33
34parser = optparse.OptionParser()
35
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 19 unchanged lines hidden (view full) ---

28
29import m5
30from m5.objects import *
31import os, optparse, sys
32m5.AddToPath('../common')
33
34parser = optparse.OptionParser()
35
36parser.add_option("--caches", action="store_true")
37parser.add_option("-t", "--timing", action="store_true")
38parser.add_option("-m", "--maxtick", type="int")
39parser.add_option("-l", "--maxloads", default = "1000000000000", type="int")
40parser.add_option("-n", "--numtesters", default = "8", type="int")
41parser.add_option("-p", "--protocol",
42 default="moesi",
43 help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)")
36parser.add_option("-c", "--cache-levels", type="int", default=2,
37 metavar="LEVELS",
38 help="Number of cache levels [default: %default]")
39parser.add_option("-a", "--atomic", action="store_true",
40 help="Use atomic (non-timing) mode")
41parser.add_option("-b", "--blocking", action="store_true",
42 help="Use blocking caches")
43parser.add_option("-l", "--maxloads", default="1G", metavar="N",
44 help="Stop after N loads [default: %default]")
45parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
46 metavar="T",
47 help="Stop after T ticks")
48parser.add_option("-n", "--numtesters", type="int", default=8,
49 metavar="N",
50 help="Number of tester pseudo-CPUs [default: %default]")
51parser.add_option("-p", "--protocol", default="moesi",
52 help="Coherence protocol [default: %default]")
44
53
54parser.add_option("-f", "--functional", type="int", default=0,
55 metavar="PCT",
56 help="Target percentage of functional accesses "
57 "[default: %default]")
58parser.add_option("-u", "--uncacheable", type="int", default=0,
59 metavar="PCT",
60 help="Target percentage of uncacheable accesses "
61 "[default: %default]")
62
45(options, args) = parser.parse_args()
46
47if args:
48 print "Error: script doesn't take any positional arguments"
49 sys.exit(1)
50
63(options, args) = parser.parse_args()
64
65if args:
66 print "Error: script doesn't take any positional arguments"
67 sys.exit(1)
68
69# Should generalize this someday... would be cool to have a loop that
70# just iterates, adding a level of caching each time.
71#if options.cache_levels != 2 and options.cache_levels != 0:
72# print "Error: number of cache levels must be 0 or 2"
73# sys.exit(1)
74
75if options.blocking:
76 num_l1_mshrs = 1
77 num_l2_mshrs = 1
78else:
79 num_l1_mshrs = 12
80 num_l2_mshrs = 92
81
82block_size = 64
83
51# --------------------
52# Base L1 Cache
53# ====================
54
55class L1(BaseCache):
56 latency = '1ns'
84# --------------------
85# Base L1 Cache
86# ====================
87
88class L1(BaseCache):
89 latency = '1ns'
57 block_size = 64
58 mshrs = 12
90 block_size = block_size
91 mshrs = num_l1_mshrs
59 tgts_per_mshr = 8
60 protocol = CoherenceProtocol(protocol=options.protocol)
61
62# ----------------------
63# Base L2 Cache
64# ----------------------
65
66class L2(BaseCache):
92 tgts_per_mshr = 8
93 protocol = CoherenceProtocol(protocol=options.protocol)
94
95# ----------------------
96# Base L2 Cache
97# ----------------------
98
99class L2(BaseCache):
67 block_size = 64
100 block_size = block_size
68 latency = '10ns'
101 latency = '10ns'
69 mshrs = 92
102 mshrs = num_l2_mshrs
70 tgts_per_mshr = 16
71 write_buffers = 8
103 tgts_per_mshr = 16
104 write_buffers = 8
105 protocol = CoherenceProtocol(protocol=options.protocol)
72
106
73#MAX CORES IS 8 with the false sharing method
74if options.numtesters > 8:
75 print "Error: NUmber of testers limited to 8 because of false sharing"
76 sys,exit(1)
107if options.numtesters > block_size:
108 print "Error: Number of testers limited to %s because of false sharing" \
109 % (block_size)
110 sys.exit(1)
77
111
78cpus = [ MemTest(atomic=not options.timing, max_loads=options.maxloads,
79 percent_functional=50, percent_uncacheable=10,
112cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
113 percent_functional=options.functional,
114 percent_uncacheable=options.uncacheable,
80 progress_interval=1000)
81 for i in xrange(options.numtesters) ]
82
83# system simulated
84system = System(cpu = cpus, funcmem = PhysicalMemory(),
115 progress_interval=1000)
116 for i in xrange(options.numtesters) ]
117
118# system simulated
119system = System(cpu = cpus, funcmem = PhysicalMemory(),
85 physmem = PhysicalMemory(latency = "50ns"), membus = Bus(clock="500MHz", width=16))
120 physmem = PhysicalMemory(latency = "100ns"),
121 membus = Bus(clock="500MHz", width=16))
86
87# l2cache & bus
122
123# l2cache & bus
88if options.caches:
124if options.cache_levels == 2:
89 system.toL2Bus = Bus(clock="500MHz", width=16)
90 system.l2c = L2(size='64kB', assoc=8)
91 system.l2c.cpu_side = system.toL2Bus.port
92
93 # connect l2c to membus
94 system.l2c.mem_side = system.membus.port
95
96# add L1 caches
97for cpu in cpus:
125 system.toL2Bus = Bus(clock="500MHz", width=16)
126 system.l2c = L2(size='64kB', assoc=8)
127 system.l2c.cpu_side = system.toL2Bus.port
128
129 # connect l2c to membus
130 system.l2c.mem_side = system.membus.port
131
132# add L1 caches
133for cpu in cpus:
98 if options.caches:
134 if options.cache_levels == 2:
99 cpu.l1c = L1(size = '32kB', assoc = 4)
100 cpu.test = cpu.l1c.cpu_side
101 cpu.l1c.mem_side = system.toL2Bus.port
135 cpu.l1c = L1(size = '32kB', assoc = 4)
136 cpu.test = cpu.l1c.cpu_side
137 cpu.l1c.mem_side = system.toL2Bus.port
138 elif options.cache_levels == 1:
139 cpu.l1c = L1(size = '32kB', assoc = 4)
140 cpu.test = cpu.l1c.cpu_side
141 cpu.l1c.mem_side = system.membus.port
102 else:
103 cpu.test = system.membus.port
104 system.funcmem.port = cpu.functional
105
106# connect memory to membus
107system.physmem.port = system.membus.port
108
109
110# -----------------------
111# run simulation
112# -----------------------
113
114root = Root( system = system )
142 else:
143 cpu.test = system.membus.port
144 system.funcmem.port = cpu.functional
145
146# connect memory to membus
147system.physmem.port = system.membus.port
148
149
150# -----------------------
151# run simulation
152# -----------------------
153
154root = Root( system = system )
115if options.timing:
116 root.system.mem_mode = 'timing'
117else:
155if options.atomic:
118 root.system.mem_mode = 'atomic'
156 root.system.mem_mode = 'atomic'
157else:
158 root.system.mem_mode = 'timing'
119
120# Not much point in this being higher than the L1 latency
121m5.ticks.setGlobalFrequency('1ns')
122
123# instantiate configuration
124m5.instantiate(root)
125
126# simulate until program terminates
159
160# Not much point in this being higher than the L1 latency
161m5.ticks.setGlobalFrequency('1ns')
162
163# instantiate configuration
164m5.instantiate(root)
165
166# simulate until program terminates
127if options.maxtick:
128 exit_event = m5.simulate(options.maxtick)
129else:
130 exit_event = m5.simulate(10000000000000)
167exit_event = m5.simulate(options.maxtick)
131
132print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
168
169print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()