memtest.py (3354:2ea739dd597c) memtest.py (3355:f15cc71cdf09)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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80 percent_uncacheable=10, progress_interval=1000)
81 for i in xrange(options.numtesters) ]
82else:
83 cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50,
84 percent_uncacheable=10, progress_interval=1000)
85 for i in xrange(options.numtesters) ]
86# system simulated
87system = System(cpu = cpus, funcmem = PhysicalMemory(),
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 71 unchanged lines hidden (view full) ---

80 percent_uncacheable=10, progress_interval=1000)
81 for i in xrange(options.numtesters) ]
82else:
83 cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50,
84 percent_uncacheable=10, progress_interval=1000)
85 for i in xrange(options.numtesters) ]
86# system simulated
87system = System(cpu = cpus, funcmem = PhysicalMemory(),
88 physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
88 physmem = PhysicalMemory(latency = "50ps"), membus = Bus(clock="500GHz", width=16))
89
90# l2cache & bus
91if options.caches:
92 system.toL2Bus = Bus(clock="500GHz", width=16)
93 system.l2c = L2(size='64kB', assoc=8)
94 system.l2c.cpu_side = system.toL2Bus.port
95
96 # connect l2c to membus

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90# l2cache & bus
91if options.caches:
92 system.toL2Bus = Bus(clock="500GHz", width=16)
93 system.l2c = L2(size='64kB', assoc=8)
94 system.l2c.cpu_side = system.toL2Bus.port
95
96 # connect l2c to membus

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