| memtest.py (12726:850e9965525b) | memtest.py (13731:67cd980cb20f) |
|---|---|
| 1# Copyright (c) 2015, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 243 unchanged lines hidden (view full) --- 252 # Scale the progress threshold as testers higher up in the tree 253 # (smaller level) get a smaller portion of the overall bandwidth, 254 # and also make the interval of packet injection longer for the 255 # testers closer to the memory (larger level) to prevent them 256 # hogging all the bandwidth 257 limit = (len(cachespec) - level + 1) * 100000000 258 testers = [proto_tester(interval = 10 * (level * level + 1), 259 progress_check = limit) \ | 1# Copyright (c) 2015, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 243 unchanged lines hidden (view full) --- 252 # Scale the progress threshold as testers higher up in the tree 253 # (smaller level) get a smaller portion of the overall bandwidth, 254 # and also make the interval of packet injection longer for the 255 # testers closer to the memory (larger level) to prevent them 256 # hogging all the bandwidth 257 limit = (len(cachespec) - level + 1) * 100000000 258 testers = [proto_tester(interval = 10 * (level * level + 1), 259 progress_check = limit) \ |
| 260 for i in xrange(ntesters)] | 260 for i in range(ntesters)] |
| 261 if ntesters: 262 subsys.tester = testers 263 264 if level != 0: 265 # Create a crossbar and add it to the subsystem, note that 266 # we do this even with a single element on this level 267 xbar = L2XBar() 268 subsys.xbar = xbar 269 if next_cache: 270 xbar.master = next_cache.cpu_side 271 272 # Create and connect the caches, both the ones fanning out 273 # to create the tree, and the ones used to connect testers 274 # on this level | 261 if ntesters: 262 subsys.tester = testers 263 264 if level != 0: 265 # Create a crossbar and add it to the subsystem, note that 266 # we do this even with a single element on this level 267 xbar = L2XBar() 268 subsys.xbar = xbar 269 if next_cache: 270 xbar.master = next_cache.cpu_side 271 272 # Create and connect the caches, both the ones fanning out 273 # to create the tree, and the ones used to connect testers 274 # on this level |
| 275 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 276 tester_caches = [proto_l1() for i in xrange(ntesters)] | 275 tree_caches = [prototypes[0]() for i in range(ncaches[0])] 276 tester_caches = [proto_l1() for i in range(ntesters)] |
| 277 278 subsys.cache = tester_caches + tree_caches 279 for cache in tree_caches: 280 cache.mem_side = xbar.slave 281 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 282 for tester, cache in zip(testers, tester_caches): 283 tester.port = cache.cpu_side 284 cache.mem_side = xbar.slave --- 50 unchanged lines hidden --- | 277 278 subsys.cache = tester_caches + tree_caches 279 for cache in tree_caches: 280 cache.mem_side = xbar.slave 281 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 282 for tester, cache in zip(testers, tester_caches): 283 tester.port = cache.cpu_side 284 cache.mem_side = xbar.slave --- 50 unchanged lines hidden --- |