| memtest.py (11272:744e6074f6ae) | memtest.py (11334:9bd2e84abdca) |
|---|---|
| 1# Copyright (c) 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 285 unchanged lines hidden (view full) --- 294 testers[0].port = next_cache.cpu_side 295 296# Top level call to create the cache hierarchy, bottom up 297make_cache_level(cachespec, cache_proto, len(cachespec), None) 298 299# Connect the lowest level crossbar to the memory 300last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 301last_subsys.xbar.master = system.physmem.port | 1# Copyright (c) 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 285 unchanged lines hidden (view full) --- 294 testers[0].port = next_cache.cpu_side 295 296# Top level call to create the cache hierarchy, bottom up 297make_cache_level(cachespec, cache_proto, len(cachespec), None) 298 299# Connect the lowest level crossbar to the memory 300last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 301last_subsys.xbar.master = system.physmem.port |
| 302last_subsys.xbar.point_of_coherency = True |
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| 302 303root = Root(full_system = False, system = system) 304if options.atomic: 305 root.system.mem_mode = 'atomic' 306else: 307 root.system.mem_mode = 'timing' 308 309# The system port is never used in the tester so merely connect it 310# to avoid problems 311root.system.system_port = last_subsys.xbar.slave 312 313# Instantiate configuration 314m5.instantiate() 315 316# Simulate until program terminates 317exit_event = m5.simulate(options.maxtick) 318 319print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() | 303 304root = Root(full_system = False, system = system) 305if options.atomic: 306 root.system.mem_mode = 'atomic' 307else: 308 root.system.mem_mode = 'timing' 309 310# The system port is never used in the tester so merely connect it 311# to avoid problems 312root.system.system_port = last_subsys.xbar.slave 313 314# Instantiate configuration 315m5.instantiate() 316 317# Simulate until program terminates 318exit_event = m5.simulate(options.maxtick) 319 320print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() |