memtest.py (10688:22452667fd5c) memtest.py (10690:4972ada74310)
1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright

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32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Andreas Hansson
28
29import optparse
30import sys
31
32import m5
33from m5.objects import *
34
35parser = optparse.OptionParser()
36
37parser.add_option("-a", "--atomic", action="store_true",
38 help="Use atomic (non-timing) mode")
39parser.add_option("-b", "--blocking", action="store_true",
40 help="Use blocking caches")
41parser.add_option("-l", "--maxloads", metavar="N", default=0,
42 help="Stop after N loads")
43parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
44 metavar="T",
45 help="Stop after T ticks")
46
41
42import optparse
43import sys
44
45import m5
46from m5.objects import *
47
48parser = optparse.OptionParser()
49
50parser.add_option("-a", "--atomic", action="store_true",
51 help="Use atomic (non-timing) mode")
52parser.add_option("-b", "--blocking", action="store_true",
53 help="Use blocking caches")
54parser.add_option("-l", "--maxloads", metavar="N", default=0,
55 help="Stop after N loads")
56parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
57 metavar="T",
58 help="Stop after T ticks")
59
60# This example script stress tests the memory system by creating false
61# sharing in a tree topology. At the bottom of the tree is a shared
62# memory, and then at each level a number of testers are attached,
63# along with a number of caches that them selves fan out to subtrees
64# of testers and caches. Thus, it is possible to create a system with
65# arbitrarily deep cache hierarchies, sharing or no sharing of caches,
66# and testers not only at the L1s, but also at the L2s, L3s etc.
47#
67#
48# The "tree" specification is a colon-separated list of one or more
49# integers. The first integer is the number of caches/testers
50# connected directly to main memory. The last integer in the list is
51# the number of testers associated with the uppermost level of memory
52# (L1 cache, if there are caches, or main memory if no caches). Thus
53# if there is only one integer, there are no caches, and the integer
54# specifies the number of testers connected directly to main memory.
55# The other integers (if any) specify the number of caches at each
56# level of the hierarchy between.
57#
58# Examples:
59#
60# "2:1" Two caches connected to memory with a single tester behind each
61# (single-level hierarchy, two testers total)
62#
63# "2:2:1" Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
64#
65parser.add_option("-t", "--treespec", type="string", default="8:1",
66 help="Colon-separated multilevel tree specification, "
68# The tree specification consists of two colon-separated lists of one
69# or more integers, one for the caches, and one for the testers. The
70# first integer is the number of caches/testers closest to main
71# memory. Each cache then fans out to a subtree. The last integer in
72# the list is the number of caches/testers associated with the
73# uppermost level of memory. The other integers (if any) specify the
74# number of caches/testers connected at each level of the crossbar
75# hierarchy. The tester string should have one element more than the
76# cache string as there should always be testers attached to the
77# uppermost caches.
78
79parser.add_option("-c", "--caches", type="string", default="2:2:1",
80 help="Colon-separated cache hierarchy specification, "
67 "see script comments for details "
68 "[default: %default]")
81 "see script comments for details "
82 "[default: %default]")
69
70parser.add_option("--force-bus", action="store_true",
71 help="Use bus between levels even with single cache")
72
83parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
84 help="Colon-separated tester hierarchy specification, "
85 "see script comments for details "
86 "[default: %default]")
73parser.add_option("-f", "--functional", type="int", default=0,
74 metavar="PCT",
75 help="Target percentage of functional accesses "
76 "[default: %default]")
77parser.add_option("-u", "--uncacheable", type="int", default=0,
78 metavar="PCT",
79 help="Target percentage of uncacheable accesses "
80 "[default: %default]")
81
87parser.add_option("-f", "--functional", type="int", default=0,
88 metavar="PCT",
89 help="Target percentage of functional accesses "
90 "[default: %default]")
91parser.add_option("-u", "--uncacheable", type="int", default=0,
92 metavar="PCT",
93 help="Target percentage of uncacheable accesses "
94 "[default: %default]")
95
82parser.add_option("--progress", type="int", default=1000,
96parser.add_option("--progress", type="int", default=10000,
83 metavar="NLOADS",
84 help="Progress message interval "
85 "[default: %default]")
86parser.add_option("--sys-clock", action="store", type="string",
87 default='1GHz',
88 help = """Top-level clock for blocks running at system
89 speed""")
90
91(options, args) = parser.parse_args()
92
93if args:
94 print "Error: script doesn't take any positional arguments"
95 sys.exit(1)
96
97block_size = 64
98
97 metavar="NLOADS",
98 help="Progress message interval "
99 "[default: %default]")
100parser.add_option("--sys-clock", action="store", type="string",
101 default='1GHz',
102 help = """Top-level clock for blocks running at system
103 speed""")
104
105(options, args) = parser.parse_args()
106
107if args:
108 print "Error: script doesn't take any positional arguments"
109 sys.exit(1)
110
111block_size = 64
112
113# Start by partins the command line options and do some basic sanity
114# checking
99try:
115try:
100 treespec = [int(x) for x in options.treespec.split(':')]
101 numtesters = reduce(lambda x,y: x*y, treespec)
116 cachespec = [int(x) for x in options.caches.split(':')]
117 testerspec = [int(x) for x in options.testers.split(':')]
102except:
118except:
103 print "Error parsing treespec option"
119 print "Error: Unable to parse caches or testers option"
104 sys.exit(1)
105
120 sys.exit(1)
121
122if len(cachespec) < 1:
123 print "Error: Must have at least one level of caches"
124 sys.exit(1)
125
126if len(cachespec) != len(testerspec) - 1:
127 print "Error: Testers must have one element more than caches"
128 sys.exit(1)
129
130if testerspec[-1] == 0:
131 print "Error: Must have testers at the uppermost level"
132 sys.exit(1)
133
134for t in testerspec:
135 if t < 0:
136 print "Error: Cannot have a negative number of testers"
137 sys.exit(1)
138
139for c in cachespec:
140 if c < 1:
141 print "Error: Must have 1 or more caches at each level"
142 sys.exit(1)
143
144# Determine the tester multiplier for each level as the string
145# elements are per subsystem and it fans out
146multiplier = [1]
147for c in cachespec:
148 if c < 1:
149 print "Error: Must have at least one cache per level"
150 multiplier.append(multiplier[-1] * c)
151
152numtesters = 0
153for t, m in zip(testerspec, multiplier):
154 numtesters += t * m
155
106if numtesters > block_size:
107 print "Error: Number of testers limited to %s because of false sharing" \
108 % (block_size)
109 sys.exit(1)
110
156if numtesters > block_size:
157 print "Error: Number of testers limited to %s because of false sharing" \
158 % (block_size)
159 sys.exit(1)
160
111if len(treespec) < 1:
112 print "Error parsing treespec"
113 sys.exit(1)
114
115# define prototype L1 cache
161# Define a prototype L1 cache that we scale for all successive levels
116proto_l1 = BaseCache(size = '32kB', assoc = 4,
117 hit_latency = 1, response_latency = 1,
162proto_l1 = BaseCache(size = '32kB', assoc = 4,
163 hit_latency = 1, response_latency = 1,
118 tgts_per_mshr = 8)
164 tgts_per_mshr = 8, is_top_level = True)
119
120if options.blocking:
121 proto_l1.mshrs = 1
122else:
123 proto_l1.mshrs = 4
124
165
166if options.blocking:
167 proto_l1.mshrs = 1
168else:
169 proto_l1.mshrs = 4
170
125# build a list of prototypes, one for each level of treespec, starting
126# at the end (last entry is tester objects)
127prototypes = [ MemTest(max_loads=options.maxloads,
128 percent_functional=options.functional,
129 percent_uncacheable=options.uncacheable,
130 progress_interval=options.progress) ]
171cache_proto = [proto_l1]
131
172
132# next comes L1 cache, if any
133if len(treespec) > 1:
134 prototypes.insert(0, proto_l1)
135
136# now add additional cache levels (if any) by scaling L1 params
137for scale in treespec[:-2]:
138 # clone previous level and update params
139 prev = prototypes[0]
173# Now add additional cache levels (if any) by scaling L1 params, the
174# first element is Ln, and the last element L1
175for scale in cachespec[:-1]:
176 # Clone previous level and update params
177 prev = cache_proto[0]
140 next = prev()
141 next.size = prev.size * scale
142 next.hit_latency = prev.hit_latency * 10
143 next.response_latency = prev.response_latency * 10
144 next.assoc = prev.assoc * scale
145 next.mshrs = prev.mshrs * scale
178 next = prev()
179 next.size = prev.size * scale
180 next.hit_latency = prev.hit_latency * 10
181 next.response_latency = prev.response_latency * 10
182 next.assoc = prev.assoc * scale
183 next.mshrs = prev.mshrs * scale
146 prototypes.insert(0, next)
184 next.is_top_level = False
185 cache_proto.insert(0, next)
147
186
148# system simulated
149system = System(physmem = SimpleMemory(latency = "100ns"),
187# Make a prototype for the tester to be used throughout
188proto_tester = MemTest(max_loads = options.maxloads,
189 percent_functional = options.functional,
190 percent_uncacheable = options.uncacheable,
191 progress_interval = options.progress)
192
193# Set up the system along with a simple memory and reference memory
194system = System(physmem = SimpleMemory(),
150 cache_line_size = block_size)
151
152system.voltage_domain = VoltageDomain(voltage = '1V')
153
154system.clk_domain = SrcClockDomain(clock = options.sys_clock,
155 voltage_domain = system.voltage_domain)
156
195 cache_line_size = block_size)
196
197system.voltage_domain = VoltageDomain(voltage = '1V')
198
199system.clk_domain = SrcClockDomain(clock = options.sys_clock,
200 voltage_domain = system.voltage_domain)
201
157def make_level(spec, prototypes, attach_obj, attach_port):
158 fanout = spec[0]
159 parent = attach_obj # use attach obj as config parent too
160 if len(spec) > 1 and (fanout > 1 or options.force_bus):
161 port = getattr(attach_obj, attach_port)
162 new_bus = CoherentXBar(width=16)
163 if (port.role == 'MASTER'):
164 new_bus.slave = port
165 attach_port = "master"
166 else:
167 new_bus.master = port
168 attach_port = "slave"
169 parent.cpu_side_bus = new_bus
170 attach_obj = new_bus
171 objs = [prototypes[0]() for i in xrange(fanout)]
172 if len(spec) > 1:
173 # we just built caches, more levels to go
174 parent.cache = objs
175 for cache in objs:
176 cache.mem_side = getattr(attach_obj, attach_port)
177 make_level(spec[1:], prototypes[1:], cache, "cpu_side")
202# For each level, track the next subsys index to use
203next_subsys_index = [0] * (len(cachespec) + 1)
204
205# Recursive function to create a sub-tree of the cache and tester
206# hierarchy
207def make_cache_level(ncaches, prototypes, level, next_cache):
208 global next_subsys_index, proto_l1, testerspec, proto_tester
209
210 index = next_subsys_index[level]
211 next_subsys_index[level] += 1
212
213 # Create a subsystem to contain the crossbar and caches, and
214 # any testers
215 subsys = SubSystem()
216 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
217
218 # The levels are indexing backwards through the list
219 ntesters = testerspec[len(cachespec) - level]
220
221 # Scale the progress threshold as testers higher up in the tree
222 # (smaller level) get a smaller portion of the overall bandwidth,
223 # and also make the interval of packet injection longer for the
224 # testers closer to the memory (larger level) to prevent them
225 # hogging all the bandwidth
226 limit = (len(cachespec) - level + 1) * 10000000
227 testers = [proto_tester(interval = 10 * (level * level + 1),
228 progress_check = limit) \
229 for i in xrange(ntesters)]
230 if ntesters:
231 subsys.tester = testers
232
233 if level != 0:
234 # Create a crossbar and add it to the subsystem, note that
235 # we do this even with a single element on this level
236 xbar = CoherentXBar(width = 32)
237 subsys.xbar = xbar
238 if next_cache:
239 xbar.master = next_cache.cpu_side
240
241 # Create and connect the caches, both the ones fanning out
242 # to create the tree, and the ones used to connect testers
243 # on this level
244 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
245 tester_caches = [proto_l1() for i in xrange(ntesters)]
246
247 subsys.cache = tester_caches + tree_caches
248 for cache in tree_caches:
249 cache.mem_side = xbar.slave
250 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
251 for tester, cache in zip(testers, tester_caches):
252 tester.port = cache.cpu_side
253 cache.mem_side = xbar.slave
178 else:
254 else:
179 # we just built the MemTest objects
180 parent.cpu = objs
181 for t in objs:
182 t.port = getattr(attach_obj, attach_port)
255 if not next_cache:
256 print "Error: No next-level cache at top level"
257 sys.exit(1)
183
258
184make_level(treespec, prototypes, system.physmem, "port")
259 if ntesters > 1:
260 # Create a crossbar and add it to the subsystem
261 xbar = CoherentXBar(width = 32)
262 subsys.xbar = xbar
263 xbar.master = next_cache.cpu_side
264 for tester in testers:
265 tester.port = xbar.slave
266 else:
267 # Single tester
268 testers[0].port = next_cache.cpu_side
185
269
186# -----------------------
187# run simulation
188# -----------------------
270# Top level call to create the cache hierarchy, bottom up
271make_cache_level(cachespec, cache_proto, len(cachespec), None)
189
272
190root = Root( full_system = False, system = system )
273# Connect the lowest level crossbar to the memory
274last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
275last_subsys.xbar.master = system.physmem.port
276
277root = Root(full_system = False, system = system)
191if options.atomic:
192 root.system.mem_mode = 'atomic'
193else:
194 root.system.mem_mode = 'timing'
195
196# The system port is never used in the tester so merely connect it
197# to avoid problems
278if options.atomic:
279 root.system.mem_mode = 'atomic'
280else:
281 root.system.mem_mode = 'timing'
282
283# The system port is never used in the tester so merely connect it
284# to avoid problems
198root.system.system_port = root.system.physmem.cpu_side_bus.slave
285root.system.system_port = last_subsys.xbar.slave
199
286
200# Not much point in this being higher than the L1 latency
201m5.ticks.setGlobalFrequency('1ns')
202
203# instantiate configuration
287# Instantiate configuration
204m5.instantiate()
205
288m5.instantiate()
289
206# simulate until program terminates
290# Simulate until program terminates
207exit_event = m5.simulate(options.maxtick)
208
209print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
291exit_event = m5.simulate(options.maxtick)
292
293print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()