| memtest.py (10270:763f76d5dea7) | memtest.py (10405:7a618c07e663) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 133 unchanged lines hidden (view full) --- 142 next.hit_latency = prev.hit_latency * 10 143 next.response_latency = prev.response_latency * 10 144 next.assoc = prev.assoc * scale 145 next.mshrs = prev.mshrs * scale 146 prototypes.insert(0, next) 147 148# system simulated 149system = System(funcmem = SimpleMemory(in_addr_map = False), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 133 unchanged lines hidden (view full) --- 142 next.hit_latency = prev.hit_latency * 10 143 next.response_latency = prev.response_latency * 10 144 next.assoc = prev.assoc * scale 145 next.mshrs = prev.mshrs * scale 146 prototypes.insert(0, next) 147 148# system simulated 149system = System(funcmem = SimpleMemory(in_addr_map = False), |
| 150 funcbus = NoncoherentBus(), | 150 funcbus = NoncoherentXBar(), |
| 151 physmem = SimpleMemory(latency = "100ns"), 152 cache_line_size = block_size) 153 154 155system.voltage_domain = VoltageDomain(voltage = '1V') 156 157system.clk_domain = SrcClockDomain(clock = options.sys_clock, 158 voltage_domain = system.voltage_domain) 159 160def make_level(spec, prototypes, attach_obj, attach_port): 161 fanout = spec[0] 162 parent = attach_obj # use attach obj as config parent too 163 if len(spec) > 1 and (fanout > 1 or options.force_bus): 164 port = getattr(attach_obj, attach_port) | 151 physmem = SimpleMemory(latency = "100ns"), 152 cache_line_size = block_size) 153 154 155system.voltage_domain = VoltageDomain(voltage = '1V') 156 157system.clk_domain = SrcClockDomain(clock = options.sys_clock, 158 voltage_domain = system.voltage_domain) 159 160def make_level(spec, prototypes, attach_obj, attach_port): 161 fanout = spec[0] 162 parent = attach_obj # use attach obj as config parent too 163 if len(spec) > 1 and (fanout > 1 or options.force_bus): 164 port = getattr(attach_obj, attach_port) |
| 165 new_bus = CoherentBus(width=16) | 165 new_bus = CoherentXBar(width=16) |
| 166 if (port.role == 'MASTER'): 167 new_bus.slave = port 168 attach_port = "master" 169 else: 170 new_bus.master = port 171 attach_port = "slave" 172 parent.cpu_side_bus = new_bus 173 attach_obj = new_bus --- 43 unchanged lines hidden --- | 166 if (port.role == 'MASTER'): 167 new_bus.slave = port 168 attach_port = "master" 169 else: 170 new_bus.master = port 171 attach_port = "slave" 172 parent.cpu_side_bus = new_bus 173 attach_obj = new_bus --- 43 unchanged lines hidden --- |