1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import optparse 30import sys 31 32import m5 33from m5.objects import * 34 35parser = optparse.OptionParser() 36 37parser.add_option("-a", "--atomic", action="store_true", 38 help="Use atomic (non-timing) mode") 39parser.add_option("-b", "--blocking", action="store_true", 40 help="Use blocking caches") 41parser.add_option("-l", "--maxloads", metavar="N", default=0, 42 help="Stop after N loads") 43parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 44 metavar="T", 45 help="Stop after T ticks") 46 47# 48# The "tree" specification is a colon-separated list of one or more 49# integers. The first integer is the number of caches/testers 50# connected directly to main memory. The last integer in the list is 51# the number of testers associated with the uppermost level of memory 52# (L1 cache, if there are caches, or main memory if no caches). Thus 53# if there is only one integer, there are no caches, and the integer 54# specifies the number of testers connected directly to main memory. 55# The other integers (if any) specify the number of caches at each 56# level of the hierarchy between. 57# 58# Examples: 59# 60# "2:1" Two caches connected to memory with a single tester behind each 61# (single-level hierarchy, two testers total) 62# 63# "2:2:1" Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total 64# 65parser.add_option("-t", "--treespec", type="string", default="8:1", 66 help="Colon-separated multilevel tree specification, " 67 "see script comments for details " 68 "[default: %default]") 69 70parser.add_option("--force-bus", action="store_true", 71 help="Use bus between levels even with single cache") 72 73parser.add_option("-f", "--functional", type="int", default=0, 74 metavar="PCT", 75 help="Target percentage of functional accesses " 76 "[default: %default]") 77parser.add_option("-u", "--uncacheable", type="int", default=0, 78 metavar="PCT", 79 help="Target percentage of uncacheable accesses " 80 "[default: %default]") 81 82parser.add_option("--progress", type="int", default=1000, 83 metavar="NLOADS", 84 help="Progress message interval " 85 "[default: %default]") 86 87(options, args) = parser.parse_args() 88 89if args: 90 print "Error: script doesn't take any positional arguments" 91 sys.exit(1) 92 93block_size = 64 94 95try: 96 treespec = [int(x) for x in options.treespec.split(':')] 97 numtesters = reduce(lambda x,y: x*y, treespec) 98except: 99 print "Error parsing treespec option" 100 sys.exit(1) 101 102if numtesters > block_size: 103 print "Error: Number of testers limited to %s because of false sharing" \ 104 % (block_size) 105 sys.exit(1) 106 107if len(treespec) < 1: 108 print "Error parsing treespec" 109 sys.exit(1) 110 111# define prototype L1 cache 112proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size, 113 latency = '1ns', tgts_per_mshr = 8) 114 115if options.blocking: 116 proto_l1.mshrs = 1 117else: 118 proto_l1.mshrs = 4 119 120# build a list of prototypes, one for each level of treespec, starting 121# at the end (last entry is tester objects) 122prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads, 123 percent_functional=options.functional, 124 percent_uncacheable=options.uncacheable, 125 progress_interval=options.progress) ] 126 127# next comes L1 cache, if any 128if len(treespec) > 1: 129 prototypes.insert(0, proto_l1) 130 131# now add additional cache levels (if any) by scaling L1 params 132for scale in treespec[:-2]: 133 # clone previous level and update params 134 prev = prototypes[0] 135 next = prev() 136 next.size = prev.size * scale 137 next.latency = prev.latency * 10 138 next.assoc = prev.assoc * scale 139 next.mshrs = prev.mshrs * scale 140 prototypes.insert(0, next) 141 142# system simulated 143system = System(funcmem = PhysicalMemory(), 144 physmem = PhysicalMemory(latency = "100ns")) 145 146def make_level(spec, prototypes, attach_obj, attach_port): 147 fanout = spec[0] 148 parent = attach_obj # use attach obj as config parent too 149 if len(spec) > 1 and (fanout > 1 or options.force_bus): 150 new_bus = Bus(clock="500MHz", width=16) 151 new_bus.port = getattr(attach_obj, attach_port) 152 parent.cpu_side_bus = new_bus 153 attach_obj = new_bus 154 attach_port = "port" 155 objs = [prototypes[0]() for i in xrange(fanout)] 156 if len(spec) > 1: 157 # we just built caches, more levels to go 158 parent.cache = objs 159 for cache in objs: 160 cache.mem_side = getattr(attach_obj, attach_port) 161 make_level(spec[1:], prototypes[1:], cache, "cpu_side") 162 else: 163 # we just built the MemTest objects 164 parent.cpu = objs 165 for t in objs: 166 t.test = getattr(attach_obj, attach_port) 167 t.functional = system.funcmem.port 168 169make_level(treespec, prototypes, system.physmem, "port") 170 171# ----------------------- 172# run simulation 173# ----------------------- 174
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