1# Copyright (c) 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# |
13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ron Dreslinski
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40# Andreas Hansson |
41 42import optparse 43import sys 44 45import m5 46from m5.objects import * 47 48parser = optparse.OptionParser() 49 50parser.add_option("-a", "--atomic", action="store_true", 51 help="Use atomic (non-timing) mode") 52parser.add_option("-b", "--blocking", action="store_true", 53 help="Use blocking caches") 54parser.add_option("-l", "--maxloads", metavar="N", default=0, 55 help="Stop after N loads") 56parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 57 metavar="T", 58 help="Stop after T ticks") 59
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60# This example script stress tests the memory system by creating false 61# sharing in a tree topology. At the bottom of the tree is a shared 62# memory, and then at each level a number of testers are attached, 63# along with a number of caches that them selves fan out to subtrees 64# of testers and caches. Thus, it is possible to create a system with 65# arbitrarily deep cache hierarchies, sharing or no sharing of caches, 66# and testers not only at the L1s, but also at the L2s, L3s etc. |
67#
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48# The "tree" specification is a colon-separated list of one or more
49# integers. The first integer is the number of caches/testers
50# connected directly to main memory. The last integer in the list is
51# the number of testers associated with the uppermost level of memory
52# (L1 cache, if there are caches, or main memory if no caches). Thus
53# if there is only one integer, there are no caches, and the integer
54# specifies the number of testers connected directly to main memory.
55# The other integers (if any) specify the number of caches at each
56# level of the hierarchy between.
57#
58# Examples:
59#
60# "2:1" Two caches connected to memory with a single tester behind each
61# (single-level hierarchy, two testers total)
62#
63# "2:2:1" Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
64#
65parser.add_option("-t", "--treespec", type="string", default="8:1",
66 help="Colon-separated multilevel tree specification, "
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68# The tree specification consists of two colon-separated lists of one 69# or more integers, one for the caches, and one for the testers. The 70# first integer is the number of caches/testers closest to main 71# memory. Each cache then fans out to a subtree. The last integer in 72# the list is the number of caches/testers associated with the 73# uppermost level of memory. The other integers (if any) specify the 74# number of caches/testers connected at each level of the crossbar 75# hierarchy. The tester string should have one element more than the 76# cache string as there should always be testers attached to the 77# uppermost caches. 78 79parser.add_option("-c", "--caches", type="string", default="2:2:1", 80 help="Colon-separated cache hierarchy specification, " |
81 "see script comments for details " 82 "[default: %default]")
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69
70parser.add_option("--force-bus", action="store_true",
71 help="Use bus between levels even with single cache")
72
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83parser.add_option("-t", "--testers", type="string", default="1:1:0:2", 84 help="Colon-separated tester hierarchy specification, " 85 "see script comments for details " 86 "[default: %default]") |
87parser.add_option("-f", "--functional", type="int", default=0, 88 metavar="PCT", 89 help="Target percentage of functional accesses " 90 "[default: %default]") 91parser.add_option("-u", "--uncacheable", type="int", default=0, 92 metavar="PCT", 93 help="Target percentage of uncacheable accesses " 94 "[default: %default]") 95
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82parser.add_option("--progress", type="int", default=1000,
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96parser.add_option("--progress", type="int", default=10000, |
97 metavar="NLOADS", 98 help="Progress message interval " 99 "[default: %default]") 100parser.add_option("--sys-clock", action="store", type="string", 101 default='1GHz', 102 help = """Top-level clock for blocks running at system 103 speed""") 104 105(options, args) = parser.parse_args() 106 107if args: 108 print "Error: script doesn't take any positional arguments" 109 sys.exit(1) 110 111block_size = 64 112
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113# Start by partins the command line options and do some basic sanity 114# checking |
115try:
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100 treespec = [int(x) for x in options.treespec.split(':')]
101 numtesters = reduce(lambda x,y: x*y, treespec)
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116 cachespec = [int(x) for x in options.caches.split(':')] 117 testerspec = [int(x) for x in options.testers.split(':')] |
118except:
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103 print "Error parsing treespec option"
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119 print "Error: Unable to parse caches or testers option" |
120 sys.exit(1) 121
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122if len(cachespec) < 1: 123 print "Error: Must have at least one level of caches" 124 sys.exit(1) 125 126if len(cachespec) != len(testerspec) - 1: 127 print "Error: Testers must have one element more than caches" 128 sys.exit(1) 129 130if testerspec[-1] == 0: 131 print "Error: Must have testers at the uppermost level" 132 sys.exit(1) 133 134for t in testerspec: 135 if t < 0: 136 print "Error: Cannot have a negative number of testers" 137 sys.exit(1) 138 139for c in cachespec: 140 if c < 1: 141 print "Error: Must have 1 or more caches at each level" 142 sys.exit(1) 143 144# Determine the tester multiplier for each level as the string 145# elements are per subsystem and it fans out 146multiplier = [1] 147for c in cachespec: 148 if c < 1: 149 print "Error: Must have at least one cache per level" 150 multiplier.append(multiplier[-1] * c) 151 152numtesters = 0 153for t, m in zip(testerspec, multiplier): 154 numtesters += t * m 155 |
156if numtesters > block_size: 157 print "Error: Number of testers limited to %s because of false sharing" \ 158 % (block_size) 159 sys.exit(1) 160
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111if len(treespec) < 1:
112 print "Error parsing treespec"
113 sys.exit(1)
114
115# define prototype L1 cache
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161# Define a prototype L1 cache that we scale for all successive levels |
162proto_l1 = BaseCache(size = '32kB', assoc = 4, 163 hit_latency = 1, response_latency = 1,
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118 tgts_per_mshr = 8)
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164 tgts_per_mshr = 8, is_top_level = True) |
165 166if options.blocking: 167 proto_l1.mshrs = 1 168else: 169 proto_l1.mshrs = 4 170
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125# build a list of prototypes, one for each level of treespec, starting
126# at the end (last entry is tester objects)
127prototypes = [ MemTest(max_loads=options.maxloads,
128 percent_functional=options.functional,
129 percent_uncacheable=options.uncacheable,
130 progress_interval=options.progress) ]
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171cache_proto = [proto_l1] |
172
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132# next comes L1 cache, if any
133if len(treespec) > 1:
134 prototypes.insert(0, proto_l1)
135
136# now add additional cache levels (if any) by scaling L1 params
137for scale in treespec[:-2]:
138 # clone previous level and update params
139 prev = prototypes[0]
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173# Now add additional cache levels (if any) by scaling L1 params, the 174# first element is Ln, and the last element L1 175for scale in cachespec[:-1]: 176 # Clone previous level and update params 177 prev = cache_proto[0] |
178 next = prev() 179 next.size = prev.size * scale 180 next.hit_latency = prev.hit_latency * 10 181 next.response_latency = prev.response_latency * 10 182 next.assoc = prev.assoc * scale 183 next.mshrs = prev.mshrs * scale
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146 prototypes.insert(0, next)
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184 next.is_top_level = False 185 cache_proto.insert(0, next) |
186
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148# system simulated
149system = System(physmem = SimpleMemory(latency = "100ns"),
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187# Make a prototype for the tester to be used throughout 188proto_tester = MemTest(max_loads = options.maxloads, 189 percent_functional = options.functional, 190 percent_uncacheable = options.uncacheable, 191 progress_interval = options.progress) 192 193# Set up the system along with a simple memory and reference memory 194system = System(physmem = SimpleMemory(), |
195 cache_line_size = block_size) 196 197system.voltage_domain = VoltageDomain(voltage = '1V') 198 199system.clk_domain = SrcClockDomain(clock = options.sys_clock, 200 voltage_domain = system.voltage_domain) 201
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157def make_level(spec, prototypes, attach_obj, attach_port):
158 fanout = spec[0]
159 parent = attach_obj # use attach obj as config parent too
160 if len(spec) > 1 and (fanout > 1 or options.force_bus):
161 port = getattr(attach_obj, attach_port)
162 new_bus = CoherentXBar(width=16)
163 if (port.role == 'MASTER'):
164 new_bus.slave = port
165 attach_port = "master"
166 else:
167 new_bus.master = port
168 attach_port = "slave"
169 parent.cpu_side_bus = new_bus
170 attach_obj = new_bus
171 objs = [prototypes[0]() for i in xrange(fanout)]
172 if len(spec) > 1:
173 # we just built caches, more levels to go
174 parent.cache = objs
175 for cache in objs:
176 cache.mem_side = getattr(attach_obj, attach_port)
177 make_level(spec[1:], prototypes[1:], cache, "cpu_side")
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202# For each level, track the next subsys index to use 203next_subsys_index = [0] * (len(cachespec) + 1) 204 205# Recursive function to create a sub-tree of the cache and tester 206# hierarchy 207def make_cache_level(ncaches, prototypes, level, next_cache): 208 global next_subsys_index, proto_l1, testerspec, proto_tester 209 210 index = next_subsys_index[level] 211 next_subsys_index[level] += 1 212 213 # Create a subsystem to contain the crossbar and caches, and 214 # any testers 215 subsys = SubSystem() 216 setattr(system, 'l%dsubsys%d' % (level, index), subsys) 217 218 # The levels are indexing backwards through the list 219 ntesters = testerspec[len(cachespec) - level] 220 221 # Scale the progress threshold as testers higher up in the tree 222 # (smaller level) get a smaller portion of the overall bandwidth, 223 # and also make the interval of packet injection longer for the 224 # testers closer to the memory (larger level) to prevent them 225 # hogging all the bandwidth 226 limit = (len(cachespec) - level + 1) * 10000000 227 testers = [proto_tester(interval = 10 * (level * level + 1), 228 progress_check = limit) \ 229 for i in xrange(ntesters)] 230 if ntesters: 231 subsys.tester = testers 232 233 if level != 0: 234 # Create a crossbar and add it to the subsystem, note that 235 # we do this even with a single element on this level 236 xbar = CoherentXBar(width = 32) 237 subsys.xbar = xbar 238 if next_cache: 239 xbar.master = next_cache.cpu_side 240 241 # Create and connect the caches, both the ones fanning out 242 # to create the tree, and the ones used to connect testers 243 # on this level 244 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 245 tester_caches = [proto_l1() for i in xrange(ntesters)] 246 247 subsys.cache = tester_caches + tree_caches 248 for cache in tree_caches: 249 cache.mem_side = xbar.slave 250 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 251 for tester, cache in zip(testers, tester_caches): 252 tester.port = cache.cpu_side 253 cache.mem_side = xbar.slave |
254 else:
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179 # we just built the MemTest objects
180 parent.cpu = objs
181 for t in objs:
182 t.port = getattr(attach_obj, attach_port)
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255 if not next_cache: 256 print "Error: No next-level cache at top level" 257 sys.exit(1) |
258
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184make_level(treespec, prototypes, system.physmem, "port")
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259 if ntesters > 1: 260 # Create a crossbar and add it to the subsystem 261 xbar = CoherentXBar(width = 32) 262 subsys.xbar = xbar 263 xbar.master = next_cache.cpu_side 264 for tester in testers: 265 tester.port = xbar.slave 266 else: 267 # Single tester 268 testers[0].port = next_cache.cpu_side |
269
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186# -----------------------
187# run simulation
188# -----------------------
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270# Top level call to create the cache hierarchy, bottom up 271make_cache_level(cachespec, cache_proto, len(cachespec), None) |
272
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190root = Root( full_system = False, system = system )
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273# Connect the lowest level crossbar to the memory 274last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 275last_subsys.xbar.master = system.physmem.port 276 277root = Root(full_system = False, system = system) |
278if options.atomic: 279 root.system.mem_mode = 'atomic' 280else: 281 root.system.mem_mode = 'timing' 282 283# The system port is never used in the tester so merely connect it 284# to avoid problems
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198root.system.system_port = root.system.physmem.cpu_side_bus.slave
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285root.system.system_port = last_subsys.xbar.slave |
286
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200# Not much point in this being higher than the L1 latency
201m5.ticks.setGlobalFrequency('1ns')
202
203# instantiate configuration
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287# Instantiate configuration |
288m5.instantiate() 289
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206# simulate until program terminates
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290# Simulate until program terminates |
291exit_event = m5.simulate(options.maxtick) 292 293print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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