1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 130 unchanged lines hidden (view full) --- 139 next.assoc = prev.assoc * scale 140 next.mshrs = prev.mshrs * scale 141 prototypes.insert(0, next) 142 143# system simulated 144system = System(funcmem = SimpleMemory(in_addr_map = False), 145 funcbus = NoncoherentBus(), 146 physmem = SimpleMemory(latency = "100ns")) |
147system.clock = options.sys_clock |
148 149def make_level(spec, prototypes, attach_obj, attach_port): 150 fanout = spec[0] 151 parent = attach_obj # use attach obj as config parent too 152 if len(spec) > 1 and (fanout > 1 or options.force_bus): 153 port = getattr(attach_obj, attach_port) 154 new_bus = CoherentBus(clock="500MHz", width=16) 155 if (port.role == 'MASTER'): --- 50 unchanged lines hidden --- |