1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 110 unchanged lines hidden (view full) --- 119 120if options.blocking: 121 proto_l1.mshrs = 1 122else: 123 proto_l1.mshrs = 4 124 125# build a list of prototypes, one for each level of treespec, starting 126# at the end (last entry is tester objects) |
127prototypes = [ MemTest(max_loads=options.maxloads, |
128 percent_functional=options.functional, 129 percent_uncacheable=options.uncacheable, 130 progress_interval=options.progress) ] 131 132# next comes L1 cache, if any 133if len(treespec) > 1: 134 prototypes.insert(0, proto_l1) 135 --- 5 unchanged lines hidden (view full) --- 141 next.size = prev.size * scale 142 next.hit_latency = prev.hit_latency * 10 143 next.response_latency = prev.response_latency * 10 144 next.assoc = prev.assoc * scale 145 next.mshrs = prev.mshrs * scale 146 prototypes.insert(0, next) 147 148# system simulated |
149system = System(physmem = SimpleMemory(latency = "100ns"), |
150 cache_line_size = block_size) 151 |
152system.voltage_domain = VoltageDomain(voltage = '1V') 153 154system.clk_domain = SrcClockDomain(clock = options.sys_clock, 155 voltage_domain = system.voltage_domain) 156 157def make_level(spec, prototypes, attach_obj, attach_port): 158 fanout = spec[0] 159 parent = attach_obj # use attach obj as config parent too --- 14 unchanged lines hidden (view full) --- 174 parent.cache = objs 175 for cache in objs: 176 cache.mem_side = getattr(attach_obj, attach_port) 177 make_level(spec[1:], prototypes[1:], cache, "cpu_side") 178 else: 179 # we just built the MemTest objects 180 parent.cpu = objs 181 for t in objs: |
182 t.port = getattr(attach_obj, attach_port) |
183 184make_level(treespec, prototypes, system.physmem, "port") 185 |
186# ----------------------- 187# run simulation 188# ----------------------- 189 190root = Root( full_system = False, system = system ) 191if options.atomic: 192 root.system.mem_mode = 'atomic' 193else: 194 root.system.mem_mode = 'timing' 195 196# The system port is never used in the tester so merely connect it 197# to avoid problems |
198root.system.system_port = root.system.physmem.cpu_side_bus.slave |
199 200# Not much point in this being higher than the L1 latency 201m5.ticks.setGlobalFrequency('1ns') 202 203# instantiate configuration 204m5.instantiate() 205 206# simulate until program terminates 207exit_event = m5.simulate(options.maxtick) 208 209print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() |