1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31import os, optparse, sys 32m5.AddToPath('../common') 33 34parser = optparse.OptionParser() 35 36parser.add_option("--caches", action="store_true") 37parser.add_option("-t", "--timing", action="store_true") 38parser.add_option("-m", "--maxtick", type="int") 39parser.add_option("-l", "--maxloads", default = "1000000000000", type="int") 40parser.add_option("-n", "--numtesters", default = "8", type="int") 41parser.add_option("-p", "--protocol", 42 default="moesi", 43 help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)") 44 45(options, args) = parser.parse_args() 46 47if args: 48 print "Error: script doesn't take any positional arguments" 49 sys.exit(1) 50 51# -------------------- 52# Base L1 Cache 53# ==================== 54 55class L1(BaseCache): 56 latency = 1 57 block_size = 64 58 mshrs = 12 59 tgts_per_mshr = 8 60 protocol = CoherenceProtocol(protocol=options.protocol) 61 62# ---------------------- 63# Base L2 Cache 64# ---------------------- 65 66class L2(BaseCache): 67 block_size = 64 68 latency = 10 69 mshrs = 92 70 tgts_per_mshr = 16 71 write_buffers = 8 72 73#MAX CORES IS 8 with the false sharing method 74if options.numtesters > 8: 75 print "Error: NUmber of testers limited to 8 because of false sharing" 76 sys,exit(1) 77 78if options.timing: 79 cpus = [ MemTest(atomic=False, max_loads=options.maxloads, percent_functional=50, 80 percent_uncacheable=10, progress_interval=1000) 81 for i in xrange(options.numtesters) ] 82else: 83 cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50, 84 percent_uncacheable=10, progress_interval=1000) 85 for i in xrange(options.numtesters) ] 86# system simulated 87system = System(cpu = cpus, funcmem = PhysicalMemory(),
| 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31import os, optparse, sys 32m5.AddToPath('../common') 33 34parser = optparse.OptionParser() 35 36parser.add_option("--caches", action="store_true") 37parser.add_option("-t", "--timing", action="store_true") 38parser.add_option("-m", "--maxtick", type="int") 39parser.add_option("-l", "--maxloads", default = "1000000000000", type="int") 40parser.add_option("-n", "--numtesters", default = "8", type="int") 41parser.add_option("-p", "--protocol", 42 default="moesi", 43 help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)") 44 45(options, args) = parser.parse_args() 46 47if args: 48 print "Error: script doesn't take any positional arguments" 49 sys.exit(1) 50 51# -------------------- 52# Base L1 Cache 53# ==================== 54 55class L1(BaseCache): 56 latency = 1 57 block_size = 64 58 mshrs = 12 59 tgts_per_mshr = 8 60 protocol = CoherenceProtocol(protocol=options.protocol) 61 62# ---------------------- 63# Base L2 Cache 64# ---------------------- 65 66class L2(BaseCache): 67 block_size = 64 68 latency = 10 69 mshrs = 92 70 tgts_per_mshr = 16 71 write_buffers = 8 72 73#MAX CORES IS 8 with the false sharing method 74if options.numtesters > 8: 75 print "Error: NUmber of testers limited to 8 because of false sharing" 76 sys,exit(1) 77 78if options.timing: 79 cpus = [ MemTest(atomic=False, max_loads=options.maxloads, percent_functional=50, 80 percent_uncacheable=10, progress_interval=1000) 81 for i in xrange(options.numtesters) ] 82else: 83 cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50, 84 percent_uncacheable=10, progress_interval=1000) 85 for i in xrange(options.numtesters) ] 86# system simulated 87system = System(cpu = cpus, funcmem = PhysicalMemory(),
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89 90# l2cache & bus 91if options.caches: 92 system.toL2Bus = Bus(clock="500GHz", width=16) 93 system.l2c = L2(size='64kB', assoc=8) 94 system.l2c.cpu_side = system.toL2Bus.port 95 96 # connect l2c to membus 97 system.l2c.mem_side = system.membus.port 98 99which_port = 0 100# add L1 caches 101for cpu in cpus: 102 if options.caches: 103 cpu.l1c = L1(size = '32kB', assoc = 4) 104 cpu.test = cpu.l1c.cpu_side 105 cpu.l1c.mem_side = system.toL2Bus.port 106 else: 107 cpu.test = system.membus.port 108 if which_port == 0: 109 system.funcmem.port = cpu.functional 110 which_port = 1 111 else: 112 system.funcmem.functional = cpu.functional 113 114 115# connect memory to membus 116system.physmem.port = system.membus.port 117 118 119# ----------------------- 120# run simulation 121# ----------------------- 122 123root = Root( system = system ) 124if options.timing: 125 root.system.mem_mode = 'timing' 126else: 127 root.system.mem_mode = 'atomic' 128 129# instantiate configuration 130m5.instantiate(root) 131 132# simulate until program terminates 133if options.maxtick: 134 exit_event = m5.simulate(options.maxtick) 135else: 136 exit_event = m5.simulate() 137 138print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
| 89 90# l2cache & bus 91if options.caches: 92 system.toL2Bus = Bus(clock="500GHz", width=16) 93 system.l2c = L2(size='64kB', assoc=8) 94 system.l2c.cpu_side = system.toL2Bus.port 95 96 # connect l2c to membus 97 system.l2c.mem_side = system.membus.port 98 99which_port = 0 100# add L1 caches 101for cpu in cpus: 102 if options.caches: 103 cpu.l1c = L1(size = '32kB', assoc = 4) 104 cpu.test = cpu.l1c.cpu_side 105 cpu.l1c.mem_side = system.toL2Bus.port 106 else: 107 cpu.test = system.membus.port 108 if which_port == 0: 109 system.funcmem.port = cpu.functional 110 which_port = 1 111 else: 112 system.funcmem.functional = cpu.functional 113 114 115# connect memory to membus 116system.physmem.port = system.membus.port 117 118 119# ----------------------- 120# run simulation 121# ----------------------- 122 123root = Root( system = system ) 124if options.timing: 125 root.system.mem_mode = 'timing' 126else: 127 root.system.mem_mode = 'atomic' 128 129# instantiate configuration 130m5.instantiate(root) 131 132# simulate until program terminates 133if options.maxtick: 134 exit_event = m5.simulate(options.maxtick) 135else: 136 exit_event = m5.simulate() 137 138print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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