1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Andreas Hansson
41
| 1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Andreas Hansson
41
|
| 42from __future__ import print_function
43
|
42import optparse
43import random
44import sys
45
46import m5
47from m5.objects import *
48
49# This example script stress tests the memory system by creating false
50# sharing in a tree topology. At the bottom of the tree is a shared
51# memory, and then at each level a number of testers are attached,
52# along with a number of caches that them selves fan out to subtrees
53# of testers and caches. Thus, it is possible to create a system with
54# arbitrarily deep cache hierarchies, sharing or no sharing of caches,
55# and testers not only at the L1s, but also at the L2s, L3s etc.
56
57parser = optparse.OptionParser()
58
59parser.add_option("-a", "--atomic", action="store_true",
60 help="Use atomic (non-timing) mode")
61parser.add_option("-b", "--blocking", action="store_true",
62 help="Use blocking caches")
63parser.add_option("-l", "--maxloads", metavar="N", default=0,
64 help="Stop after N loads")
65parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
66 metavar="T",
67 help="Stop after T ticks")
68
69# The tree specification consists of two colon-separated lists of one
70# or more integers, one for the caches, and one for the testers. The
71# first integer is the number of caches/testers closest to main
72# memory. Each cache then fans out to a subtree. The last integer in
73# the list is the number of caches/testers associated with the
74# uppermost level of memory. The other integers (if any) specify the
75# number of caches/testers connected at each level of the crossbar
76# hierarchy. The tester string should have one element more than the
77# cache string as there should always be testers attached to the
78# uppermost caches.
79
80parser.add_option("-c", "--caches", type="string", default="2:2:1",
81 help="Colon-separated cache hierarchy specification, "
82 "see script comments for details "
83 "[default: %default]")
84parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
85 help="Colon-separated tester hierarchy specification, "
86 "see script comments for details "
87 "[default: %default]")
88parser.add_option("-f", "--functional", type="int", default=10,
89 metavar="PCT",
90 help="Target percentage of functional accesses "
91 "[default: %default]")
92parser.add_option("-u", "--uncacheable", type="int", default=10,
93 metavar="PCT",
94 help="Target percentage of uncacheable accesses "
95 "[default: %default]")
96parser.add_option("-r", "--random", action="store_true",
97 help="Generate a random tree topology")
98parser.add_option("--progress", type="int", default=100000,
99 metavar="NLOADS",
100 help="Progress message interval "
101 "[default: %default]")
102parser.add_option("--sys-clock", action="store", type="string",
103 default='1GHz',
104 help = """Top-level clock for blocks running at system
105 speed""")
106
107(options, args) = parser.parse_args()
108
109if args:
| 44import optparse
45import random
46import sys
47
48import m5
49from m5.objects import *
50
51# This example script stress tests the memory system by creating false
52# sharing in a tree topology. At the bottom of the tree is a shared
53# memory, and then at each level a number of testers are attached,
54# along with a number of caches that them selves fan out to subtrees
55# of testers and caches. Thus, it is possible to create a system with
56# arbitrarily deep cache hierarchies, sharing or no sharing of caches,
57# and testers not only at the L1s, but also at the L2s, L3s etc.
58
59parser = optparse.OptionParser()
60
61parser.add_option("-a", "--atomic", action="store_true",
62 help="Use atomic (non-timing) mode")
63parser.add_option("-b", "--blocking", action="store_true",
64 help="Use blocking caches")
65parser.add_option("-l", "--maxloads", metavar="N", default=0,
66 help="Stop after N loads")
67parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
68 metavar="T",
69 help="Stop after T ticks")
70
71# The tree specification consists of two colon-separated lists of one
72# or more integers, one for the caches, and one for the testers. The
73# first integer is the number of caches/testers closest to main
74# memory. Each cache then fans out to a subtree. The last integer in
75# the list is the number of caches/testers associated with the
76# uppermost level of memory. The other integers (if any) specify the
77# number of caches/testers connected at each level of the crossbar
78# hierarchy. The tester string should have one element more than the
79# cache string as there should always be testers attached to the
80# uppermost caches.
81
82parser.add_option("-c", "--caches", type="string", default="2:2:1",
83 help="Colon-separated cache hierarchy specification, "
84 "see script comments for details "
85 "[default: %default]")
86parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
87 help="Colon-separated tester hierarchy specification, "
88 "see script comments for details "
89 "[default: %default]")
90parser.add_option("-f", "--functional", type="int", default=10,
91 metavar="PCT",
92 help="Target percentage of functional accesses "
93 "[default: %default]")
94parser.add_option("-u", "--uncacheable", type="int", default=10,
95 metavar="PCT",
96 help="Target percentage of uncacheable accesses "
97 "[default: %default]")
98parser.add_option("-r", "--random", action="store_true",
99 help="Generate a random tree topology")
100parser.add_option("--progress", type="int", default=100000,
101 metavar="NLOADS",
102 help="Progress message interval "
103 "[default: %default]")
104parser.add_option("--sys-clock", action="store", type="string",
105 default='1GHz',
106 help = """Top-level clock for blocks running at system
107 speed""")
108
109(options, args) = parser.parse_args()
110
111if args:
|
110 print "Error: script doesn't take any positional arguments"
| 112 print("Error: script doesn't take any positional arguments")
|
111 sys.exit(1)
112
113# Get the total number of testers
114def numtesters(cachespec, testerspec):
115 # Determine the tester multiplier for each level as the
116 # elements are per subsystem and it fans out
117 multiplier = [1]
118 for c in cachespec:
119 multiplier.append(multiplier[-1] * c)
120
121 total = 0
122 for t, m in zip(testerspec, multiplier):
123 total += t * m
124
125 return total
126
127block_size = 64
128
129# Start by parsing the command line options and do some basic sanity
130# checking
131if options.random:
132 # Generate a tree with a valid number of testers
133 while True:
134 tree_depth = random.randint(1, 4)
135 cachespec = [random.randint(1, 3) for i in range(tree_depth)]
136 testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
137 if numtesters(cachespec, testerspec) < block_size:
138 break
139
| 113 sys.exit(1)
114
115# Get the total number of testers
116def numtesters(cachespec, testerspec):
117 # Determine the tester multiplier for each level as the
118 # elements are per subsystem and it fans out
119 multiplier = [1]
120 for c in cachespec:
121 multiplier.append(multiplier[-1] * c)
122
123 total = 0
124 for t, m in zip(testerspec, multiplier):
125 total += t * m
126
127 return total
128
129block_size = 64
130
131# Start by parsing the command line options and do some basic sanity
132# checking
133if options.random:
134 # Generate a tree with a valid number of testers
135 while True:
136 tree_depth = random.randint(1, 4)
137 cachespec = [random.randint(1, 3) for i in range(tree_depth)]
138 testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
139 if numtesters(cachespec, testerspec) < block_size:
140 break
141
|
140 print "Generated random tree -c", ':'.join(map(str, cachespec)), \
141 "-t", ':'.join(map(str, testerspec))
| 142 print("Generated random tree -c", ':'.join(map(str, cachespec)),
143 "-t", ':'.join(map(str, testerspec)))
|
142else:
143 try:
144 cachespec = [int(x) for x in options.caches.split(':')]
145 testerspec = [int(x) for x in options.testers.split(':')]
146 except:
| 144else:
145 try:
146 cachespec = [int(x) for x in options.caches.split(':')]
147 testerspec = [int(x) for x in options.testers.split(':')]
148 except:
|
147 print "Error: Unable to parse caches or testers option"
| 149 print("Error: Unable to parse caches or testers option")
|
148 sys.exit(1)
149
150 if len(cachespec) < 1:
| 150 sys.exit(1)
151
152 if len(cachespec) < 1:
|
151 print "Error: Must have at least one level of caches"
| 153 print("Error: Must have at least one level of caches")
|
152 sys.exit(1)
153
154 if len(cachespec) != len(testerspec) - 1:
| 154 sys.exit(1)
155
156 if len(cachespec) != len(testerspec) - 1:
|
155 print "Error: Testers must have one element more than caches"
| 157 print("Error: Testers must have one element more than caches")
|
156 sys.exit(1)
157
158 if testerspec[-1] == 0:
| 158 sys.exit(1)
159
160 if testerspec[-1] == 0:
|
159 print "Error: Must have testers at the uppermost level"
| 161 print("Error: Must have testers at the uppermost level")
|
160 sys.exit(1)
161
162 for t in testerspec:
163 if t < 0:
| 162 sys.exit(1)
163
164 for t in testerspec:
165 if t < 0:
|
164 print "Error: Cannot have a negative number of testers"
| 166 print("Error: Cannot have a negative number of testers")
|
165 sys.exit(1)
166
167 for c in cachespec:
168 if c < 1:
| 167 sys.exit(1)
168
169 for c in cachespec:
170 if c < 1:
|
169 print "Error: Must have 1 or more caches at each level"
| 171 print("Error: Must have 1 or more caches at each level")
|
170 sys.exit(1)
171
172 if numtesters(cachespec, testerspec) > block_size:
| 172 sys.exit(1)
173
174 if numtesters(cachespec, testerspec) > block_size:
|
173 print "Error: Limited to %s testers because of false sharing" \
174 % (block_size)
| 175 print("Error: Limited to %s testers because of false sharing"
176 % (block_size))
|
175 sys.exit(1)
176
177# Define a prototype L1 cache that we scale for all successive levels
178proto_l1 = Cache(size = '32kB', assoc = 4,
179 tag_latency = 1, data_latency = 1, response_latency = 1,
180 tgts_per_mshr = 8, clusivity = 'mostly_incl',
181 writeback_clean = True)
182
183if options.blocking:
184 proto_l1.mshrs = 1
185else:
186 proto_l1.mshrs = 4
187
188cache_proto = [proto_l1]
189
190# Now add additional cache levels (if any) by scaling L1 params, the
191# first element is Ln, and the last element L1
192for scale in cachespec[:-1]:
193 # Clone previous level and update params
194 prev = cache_proto[0]
195 next = prev()
196 next.size = prev.size * scale
197 next.tag_latency = prev.tag_latency * 10
198 next.data_latency = prev.data_latency * 10
199 next.response_latency = prev.response_latency * 10
200 next.assoc = prev.assoc * scale
201 next.mshrs = prev.mshrs * scale
202
203 # Swap the inclusivity/exclusivity at each level. L2 is mostly
204 # exclusive with respect to L1, L3 mostly inclusive, L4 mostly
205 # exclusive etc.
206 next.writeback_clean = not prev.writeback_clean
207 if (prev.clusivity.value == 'mostly_incl'):
208 next.clusivity = 'mostly_excl'
209 else:
210 next.clusivity = 'mostly_incl'
211
212 cache_proto.insert(0, next)
213
214# Make a prototype for the tester to be used throughout
215proto_tester = MemTest(max_loads = options.maxloads,
216 percent_functional = options.functional,
217 percent_uncacheable = options.uncacheable,
218 progress_interval = options.progress)
219
220# Set up the system along with a simple memory and reference memory
221system = System(physmem = SimpleMemory(),
222 cache_line_size = block_size)
223
224system.voltage_domain = VoltageDomain(voltage = '1V')
225
226system.clk_domain = SrcClockDomain(clock = options.sys_clock,
227 voltage_domain = system.voltage_domain)
228
229# For each level, track the next subsys index to use
230next_subsys_index = [0] * (len(cachespec) + 1)
231
232# Recursive function to create a sub-tree of the cache and tester
233# hierarchy
234def make_cache_level(ncaches, prototypes, level, next_cache):
235 global next_subsys_index, proto_l1, testerspec, proto_tester
236
237 index = next_subsys_index[level]
238 next_subsys_index[level] += 1
239
240 # Create a subsystem to contain the crossbar and caches, and
241 # any testers
242 subsys = SubSystem()
243 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
244
245 # The levels are indexing backwards through the list
246 ntesters = testerspec[len(cachespec) - level]
247
248 # Scale the progress threshold as testers higher up in the tree
249 # (smaller level) get a smaller portion of the overall bandwidth,
250 # and also make the interval of packet injection longer for the
251 # testers closer to the memory (larger level) to prevent them
252 # hogging all the bandwidth
253 limit = (len(cachespec) - level + 1) * 100000000
254 testers = [proto_tester(interval = 10 * (level * level + 1),
255 progress_check = limit) \
256 for i in xrange(ntesters)]
257 if ntesters:
258 subsys.tester = testers
259
260 if level != 0:
261 # Create a crossbar and add it to the subsystem, note that
262 # we do this even with a single element on this level
263 xbar = L2XBar()
264 subsys.xbar = xbar
265 if next_cache:
266 xbar.master = next_cache.cpu_side
267
268 # Create and connect the caches, both the ones fanning out
269 # to create the tree, and the ones used to connect testers
270 # on this level
271 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
272 tester_caches = [proto_l1() for i in xrange(ntesters)]
273
274 subsys.cache = tester_caches + tree_caches
275 for cache in tree_caches:
276 cache.mem_side = xbar.slave
277 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
278 for tester, cache in zip(testers, tester_caches):
279 tester.port = cache.cpu_side
280 cache.mem_side = xbar.slave
281 else:
282 if not next_cache:
| 177 sys.exit(1)
178
179# Define a prototype L1 cache that we scale for all successive levels
180proto_l1 = Cache(size = '32kB', assoc = 4,
181 tag_latency = 1, data_latency = 1, response_latency = 1,
182 tgts_per_mshr = 8, clusivity = 'mostly_incl',
183 writeback_clean = True)
184
185if options.blocking:
186 proto_l1.mshrs = 1
187else:
188 proto_l1.mshrs = 4
189
190cache_proto = [proto_l1]
191
192# Now add additional cache levels (if any) by scaling L1 params, the
193# first element is Ln, and the last element L1
194for scale in cachespec[:-1]:
195 # Clone previous level and update params
196 prev = cache_proto[0]
197 next = prev()
198 next.size = prev.size * scale
199 next.tag_latency = prev.tag_latency * 10
200 next.data_latency = prev.data_latency * 10
201 next.response_latency = prev.response_latency * 10
202 next.assoc = prev.assoc * scale
203 next.mshrs = prev.mshrs * scale
204
205 # Swap the inclusivity/exclusivity at each level. L2 is mostly
206 # exclusive with respect to L1, L3 mostly inclusive, L4 mostly
207 # exclusive etc.
208 next.writeback_clean = not prev.writeback_clean
209 if (prev.clusivity.value == 'mostly_incl'):
210 next.clusivity = 'mostly_excl'
211 else:
212 next.clusivity = 'mostly_incl'
213
214 cache_proto.insert(0, next)
215
216# Make a prototype for the tester to be used throughout
217proto_tester = MemTest(max_loads = options.maxloads,
218 percent_functional = options.functional,
219 percent_uncacheable = options.uncacheable,
220 progress_interval = options.progress)
221
222# Set up the system along with a simple memory and reference memory
223system = System(physmem = SimpleMemory(),
224 cache_line_size = block_size)
225
226system.voltage_domain = VoltageDomain(voltage = '1V')
227
228system.clk_domain = SrcClockDomain(clock = options.sys_clock,
229 voltage_domain = system.voltage_domain)
230
231# For each level, track the next subsys index to use
232next_subsys_index = [0] * (len(cachespec) + 1)
233
234# Recursive function to create a sub-tree of the cache and tester
235# hierarchy
236def make_cache_level(ncaches, prototypes, level, next_cache):
237 global next_subsys_index, proto_l1, testerspec, proto_tester
238
239 index = next_subsys_index[level]
240 next_subsys_index[level] += 1
241
242 # Create a subsystem to contain the crossbar and caches, and
243 # any testers
244 subsys = SubSystem()
245 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
246
247 # The levels are indexing backwards through the list
248 ntesters = testerspec[len(cachespec) - level]
249
250 # Scale the progress threshold as testers higher up in the tree
251 # (smaller level) get a smaller portion of the overall bandwidth,
252 # and also make the interval of packet injection longer for the
253 # testers closer to the memory (larger level) to prevent them
254 # hogging all the bandwidth
255 limit = (len(cachespec) - level + 1) * 100000000
256 testers = [proto_tester(interval = 10 * (level * level + 1),
257 progress_check = limit) \
258 for i in xrange(ntesters)]
259 if ntesters:
260 subsys.tester = testers
261
262 if level != 0:
263 # Create a crossbar and add it to the subsystem, note that
264 # we do this even with a single element on this level
265 xbar = L2XBar()
266 subsys.xbar = xbar
267 if next_cache:
268 xbar.master = next_cache.cpu_side
269
270 # Create and connect the caches, both the ones fanning out
271 # to create the tree, and the ones used to connect testers
272 # on this level
273 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
274 tester_caches = [proto_l1() for i in xrange(ntesters)]
275
276 subsys.cache = tester_caches + tree_caches
277 for cache in tree_caches:
278 cache.mem_side = xbar.slave
279 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
280 for tester, cache in zip(testers, tester_caches):
281 tester.port = cache.cpu_side
282 cache.mem_side = xbar.slave
283 else:
284 if not next_cache:
|
283 print "Error: No next-level cache at top level"
| 285 print("Error: No next-level cache at top level")
|
284 sys.exit(1)
285
286 if ntesters > 1:
287 # Create a crossbar and add it to the subsystem
288 xbar = L2XBar()
289 subsys.xbar = xbar
290 xbar.master = next_cache.cpu_side
291 for tester in testers:
292 tester.port = xbar.slave
293 else:
294 # Single tester
295 testers[0].port = next_cache.cpu_side
296
297# Top level call to create the cache hierarchy, bottom up
298make_cache_level(cachespec, cache_proto, len(cachespec), None)
299
300# Connect the lowest level crossbar to the memory
301last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
302last_subsys.xbar.master = system.physmem.port
303last_subsys.xbar.point_of_coherency = True
304
305root = Root(full_system = False, system = system)
306if options.atomic:
307 root.system.mem_mode = 'atomic'
308else:
309 root.system.mem_mode = 'timing'
310
311# The system port is never used in the tester so merely connect it
312# to avoid problems
313root.system.system_port = last_subsys.xbar.slave
314
315# Instantiate configuration
316m5.instantiate()
317
318# Simulate until program terminates
319exit_event = m5.simulate(options.maxtick)
320
| 286 sys.exit(1)
287
288 if ntesters > 1:
289 # Create a crossbar and add it to the subsystem
290 xbar = L2XBar()
291 subsys.xbar = xbar
292 xbar.master = next_cache.cpu_side
293 for tester in testers:
294 tester.port = xbar.slave
295 else:
296 # Single tester
297 testers[0].port = next_cache.cpu_side
298
299# Top level call to create the cache hierarchy, bottom up
300make_cache_level(cachespec, cache_proto, len(cachespec), None)
301
302# Connect the lowest level crossbar to the memory
303last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
304last_subsys.xbar.master = system.physmem.port
305last_subsys.xbar.point_of_coherency = True
306
307root = Root(full_system = False, system = system)
308if options.atomic:
309 root.system.mem_mode = 'atomic'
310else:
311 root.system.mem_mode = 'timing'
312
313# The system port is never used in the tester so merely connect it
314# to avoid problems
315root.system.system_port = last_subsys.xbar.slave
316
317# Instantiate configuration
318m5.instantiate()
319
320# Simulate until program terminates
321exit_event = m5.simulate(options.maxtick)
322
|
321print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
| 323print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
|
| |