1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Andreas Hansson
41
42import optparse
| 1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ron Dreslinski
40# Andreas Hansson
41
42import optparse
|
| 43import random
|
43import sys
44
45import m5
46from m5.objects import *
47
| 44import sys
45
46import m5
47from m5.objects import *
48
|
| 49# This example script stress tests the memory system by creating false
50# sharing in a tree topology. At the bottom of the tree is a shared
51# memory, and then at each level a number of testers are attached,
52# along with a number of caches that them selves fan out to subtrees
53# of testers and caches. Thus, it is possible to create a system with
54# arbitrarily deep cache hierarchies, sharing or no sharing of caches,
55# and testers not only at the L1s, but also at the L2s, L3s etc.
56
|
48parser = optparse.OptionParser()
49
50parser.add_option("-a", "--atomic", action="store_true",
51 help="Use atomic (non-timing) mode")
52parser.add_option("-b", "--blocking", action="store_true",
53 help="Use blocking caches")
54parser.add_option("-l", "--maxloads", metavar="N", default=0,
55 help="Stop after N loads")
56parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
57 metavar="T",
58 help="Stop after T ticks")
59
| 57parser = optparse.OptionParser()
58
59parser.add_option("-a", "--atomic", action="store_true",
60 help="Use atomic (non-timing) mode")
61parser.add_option("-b", "--blocking", action="store_true",
62 help="Use blocking caches")
63parser.add_option("-l", "--maxloads", metavar="N", default=0,
64 help="Stop after N loads")
65parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
66 metavar="T",
67 help="Stop after T ticks")
68
|
60# This example script stress tests the memory system by creating false
61# sharing in a tree topology. At the bottom of the tree is a shared
62# memory, and then at each level a number of testers are attached,
63# along with a number of caches that them selves fan out to subtrees
64# of testers and caches. Thus, it is possible to create a system with
65# arbitrarily deep cache hierarchies, sharing or no sharing of caches,
66# and testers not only at the L1s, but also at the L2s, L3s etc.
67#
| |
68# The tree specification consists of two colon-separated lists of one
69# or more integers, one for the caches, and one for the testers. The
70# first integer is the number of caches/testers closest to main
71# memory. Each cache then fans out to a subtree. The last integer in
72# the list is the number of caches/testers associated with the
73# uppermost level of memory. The other integers (if any) specify the
74# number of caches/testers connected at each level of the crossbar
75# hierarchy. The tester string should have one element more than the
76# cache string as there should always be testers attached to the
77# uppermost caches.
78
79parser.add_option("-c", "--caches", type="string", default="2:2:1",
80 help="Colon-separated cache hierarchy specification, "
81 "see script comments for details "
82 "[default: %default]")
83parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
84 help="Colon-separated tester hierarchy specification, "
85 "see script comments for details "
86 "[default: %default]")
87parser.add_option("-f", "--functional", type="int", default=0,
88 metavar="PCT",
89 help="Target percentage of functional accesses "
90 "[default: %default]")
91parser.add_option("-u", "--uncacheable", type="int", default=0,
92 metavar="PCT",
93 help="Target percentage of uncacheable accesses "
94 "[default: %default]")
| 69# The tree specification consists of two colon-separated lists of one
70# or more integers, one for the caches, and one for the testers. The
71# first integer is the number of caches/testers closest to main
72# memory. Each cache then fans out to a subtree. The last integer in
73# the list is the number of caches/testers associated with the
74# uppermost level of memory. The other integers (if any) specify the
75# number of caches/testers connected at each level of the crossbar
76# hierarchy. The tester string should have one element more than the
77# cache string as there should always be testers attached to the
78# uppermost caches.
79
80parser.add_option("-c", "--caches", type="string", default="2:2:1",
81 help="Colon-separated cache hierarchy specification, "
82 "see script comments for details "
83 "[default: %default]")
84parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
85 help="Colon-separated tester hierarchy specification, "
86 "see script comments for details "
87 "[default: %default]")
88parser.add_option("-f", "--functional", type="int", default=0,
89 metavar="PCT",
90 help="Target percentage of functional accesses "
91 "[default: %default]")
92parser.add_option("-u", "--uncacheable", type="int", default=0,
93 metavar="PCT",
94 help="Target percentage of uncacheable accesses "
95 "[default: %default]")
|
95
96parser.add_option("--progress", type="int", default=10000,
| 96parser.add_option("-r", "--random", action="store_true",
97 help="Generate a random tree topology")
98parser.add_option("--progress", type="int", default=100000,
|
97 metavar="NLOADS",
98 help="Progress message interval "
99 "[default: %default]")
100parser.add_option("--sys-clock", action="store", type="string",
101 default='1GHz',
102 help = """Top-level clock for blocks running at system
103 speed""")
104
105(options, args) = parser.parse_args()
106
107if args:
108 print "Error: script doesn't take any positional arguments"
109 sys.exit(1)
110
| 99 metavar="NLOADS",
100 help="Progress message interval "
101 "[default: %default]")
102parser.add_option("--sys-clock", action="store", type="string",
103 default='1GHz',
104 help = """Top-level clock for blocks running at system
105 speed""")
106
107(options, args) = parser.parse_args()
108
109if args:
110 print "Error: script doesn't take any positional arguments"
111 sys.exit(1)
112
|
| 113# Get the total number of testers
114def numtesters(cachespec, testerspec):
115 # Determine the tester multiplier for each level as the
116 # elements are per subsystem and it fans out
117 multiplier = [1]
118 for c in cachespec:
119 multiplier.append(multiplier[-1] * c)
120
121 total = 0
122 for t, m in zip(testerspec, multiplier):
123 total += t * m
124
125 return total
126
|
111block_size = 64
112
113# Start by parsing the command line options and do some basic sanity
114# checking
| 127block_size = 64
128
129# Start by parsing the command line options and do some basic sanity
130# checking
|
115try:
116 cachespec = [int(x) for x in options.caches.split(':')]
117 testerspec = [int(x) for x in options.testers.split(':')]
118except:
119 print "Error: Unable to parse caches or testers option"
120 sys.exit(1)
| 131if options.random:
132 # Generate a tree with a valid number of testers
133 while True:
134 tree_depth = random.randint(1, 4)
135 cachespec = [random.randint(1, 3) for i in range(tree_depth)]
136 testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
137 if numtesters(cachespec, testerspec) < block_size:
138 break
|
121
| 139
|
122if len(cachespec) < 1:
123 print "Error: Must have at least one level of caches"
124 sys.exit(1)
| 140 print "Generated random tree -c", ':'.join(map(str, cachespec)), \
141 "-t", ':'.join(map(str, testerspec))
142else:
143 try:
144 cachespec = [int(x) for x in options.caches.split(':')]
145 testerspec = [int(x) for x in options.testers.split(':')]
146 except:
147 print "Error: Unable to parse caches or testers option"
148 sys.exit(1)
|
125
| 149
|
126if len(cachespec) != len(testerspec) - 1:
127 print "Error: Testers must have one element more than caches"
128 sys.exit(1)
| 150 if len(cachespec) < 1:
151 print "Error: Must have at least one level of caches"
152 sys.exit(1)
|
129
| 153
|
130if testerspec[-1] == 0:
131 print "Error: Must have testers at the uppermost level"
132 sys.exit(1)
133
134for t in testerspec:
135 if t < 0:
136 print "Error: Cannot have a negative number of testers"
| 154 if len(cachespec) != len(testerspec) - 1:
155 print "Error: Testers must have one element more than caches"
|
137 sys.exit(1)
138
| 156 sys.exit(1)
157
|
139for c in cachespec:
140 if c < 1:
141 print "Error: Must have 1 or more caches at each level"
| 158 if testerspec[-1] == 0:
159 print "Error: Must have testers at the uppermost level"
|
142 sys.exit(1)
143
| 160 sys.exit(1)
161
|
144# Determine the tester multiplier for each level as the string
145# elements are per subsystem and it fans out
146multiplier = [1]
147for c in cachespec:
148 if c < 1:
149 print "Error: Must have at least one cache per level"
150 multiplier.append(multiplier[-1] * c)
| 162 for t in testerspec:
163 if t < 0:
164 print "Error: Cannot have a negative number of testers"
165 sys.exit(1)
|
151
| 166
|
152numtesters = 0
153for t, m in zip(testerspec, multiplier):
154 numtesters += t * m
| 167 for c in cachespec:
168 if c < 1:
169 print "Error: Must have 1 or more caches at each level"
170 sys.exit(1)
|
155
| 171
|
156if numtesters > block_size:
157 print "Error: Number of testers limited to %s because of false sharing" \
158 % (block_size)
159 sys.exit(1)
| 172 if numtesters(cachespec, testerspec) > block_size:
173 print "Error: Limited to %s testers because of false sharing" \
174 % (block_size)
175 sys.exit(1)
|
160
161# Define a prototype L1 cache that we scale for all successive levels
162proto_l1 = BaseCache(size = '32kB', assoc = 4,
163 hit_latency = 1, response_latency = 1,
164 tgts_per_mshr = 8, is_top_level = True)
165
166if options.blocking:
167 proto_l1.mshrs = 1
168else:
169 proto_l1.mshrs = 4
170
171cache_proto = [proto_l1]
172
173# Now add additional cache levels (if any) by scaling L1 params, the
174# first element is Ln, and the last element L1
175for scale in cachespec[:-1]:
176 # Clone previous level and update params
177 prev = cache_proto[0]
178 next = prev()
179 next.size = prev.size * scale
180 next.hit_latency = prev.hit_latency * 10
181 next.response_latency = prev.response_latency * 10
182 next.assoc = prev.assoc * scale
183 next.mshrs = prev.mshrs * scale
184 next.is_top_level = False
185 cache_proto.insert(0, next)
186
187# Make a prototype for the tester to be used throughout
188proto_tester = MemTest(max_loads = options.maxloads,
189 percent_functional = options.functional,
190 percent_uncacheable = options.uncacheable,
191 progress_interval = options.progress)
192
193# Set up the system along with a simple memory and reference memory
194system = System(physmem = SimpleMemory(),
195 cache_line_size = block_size)
196
197system.voltage_domain = VoltageDomain(voltage = '1V')
198
199system.clk_domain = SrcClockDomain(clock = options.sys_clock,
200 voltage_domain = system.voltage_domain)
201
202# For each level, track the next subsys index to use
203next_subsys_index = [0] * (len(cachespec) + 1)
204
205# Recursive function to create a sub-tree of the cache and tester
206# hierarchy
207def make_cache_level(ncaches, prototypes, level, next_cache):
208 global next_subsys_index, proto_l1, testerspec, proto_tester
209
210 index = next_subsys_index[level]
211 next_subsys_index[level] += 1
212
213 # Create a subsystem to contain the crossbar and caches, and
214 # any testers
215 subsys = SubSystem()
216 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
217
218 # The levels are indexing backwards through the list
219 ntesters = testerspec[len(cachespec) - level]
220
221 # Scale the progress threshold as testers higher up in the tree
222 # (smaller level) get a smaller portion of the overall bandwidth,
223 # and also make the interval of packet injection longer for the
224 # testers closer to the memory (larger level) to prevent them
225 # hogging all the bandwidth
| 176
177# Define a prototype L1 cache that we scale for all successive levels
178proto_l1 = BaseCache(size = '32kB', assoc = 4,
179 hit_latency = 1, response_latency = 1,
180 tgts_per_mshr = 8, is_top_level = True)
181
182if options.blocking:
183 proto_l1.mshrs = 1
184else:
185 proto_l1.mshrs = 4
186
187cache_proto = [proto_l1]
188
189# Now add additional cache levels (if any) by scaling L1 params, the
190# first element is Ln, and the last element L1
191for scale in cachespec[:-1]:
192 # Clone previous level and update params
193 prev = cache_proto[0]
194 next = prev()
195 next.size = prev.size * scale
196 next.hit_latency = prev.hit_latency * 10
197 next.response_latency = prev.response_latency * 10
198 next.assoc = prev.assoc * scale
199 next.mshrs = prev.mshrs * scale
200 next.is_top_level = False
201 cache_proto.insert(0, next)
202
203# Make a prototype for the tester to be used throughout
204proto_tester = MemTest(max_loads = options.maxloads,
205 percent_functional = options.functional,
206 percent_uncacheable = options.uncacheable,
207 progress_interval = options.progress)
208
209# Set up the system along with a simple memory and reference memory
210system = System(physmem = SimpleMemory(),
211 cache_line_size = block_size)
212
213system.voltage_domain = VoltageDomain(voltage = '1V')
214
215system.clk_domain = SrcClockDomain(clock = options.sys_clock,
216 voltage_domain = system.voltage_domain)
217
218# For each level, track the next subsys index to use
219next_subsys_index = [0] * (len(cachespec) + 1)
220
221# Recursive function to create a sub-tree of the cache and tester
222# hierarchy
223def make_cache_level(ncaches, prototypes, level, next_cache):
224 global next_subsys_index, proto_l1, testerspec, proto_tester
225
226 index = next_subsys_index[level]
227 next_subsys_index[level] += 1
228
229 # Create a subsystem to contain the crossbar and caches, and
230 # any testers
231 subsys = SubSystem()
232 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
233
234 # The levels are indexing backwards through the list
235 ntesters = testerspec[len(cachespec) - level]
236
237 # Scale the progress threshold as testers higher up in the tree
238 # (smaller level) get a smaller portion of the overall bandwidth,
239 # and also make the interval of packet injection longer for the
240 # testers closer to the memory (larger level) to prevent them
241 # hogging all the bandwidth
|
226 limit = (len(cachespec) - level + 1) * 10000000
| 242 limit = (len(cachespec) - level + 1) * 100000000
|
227 testers = [proto_tester(interval = 10 * (level * level + 1),
228 progress_check = limit) \
229 for i in xrange(ntesters)]
230 if ntesters:
231 subsys.tester = testers
232
233 if level != 0:
234 # Create a crossbar and add it to the subsystem, note that
235 # we do this even with a single element on this level
236 xbar = L2XBar()
237 subsys.xbar = xbar
238 if next_cache:
239 xbar.master = next_cache.cpu_side
240
241 # Create and connect the caches, both the ones fanning out
242 # to create the tree, and the ones used to connect testers
243 # on this level
244 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
245 tester_caches = [proto_l1() for i in xrange(ntesters)]
246
247 subsys.cache = tester_caches + tree_caches
248 for cache in tree_caches:
249 cache.mem_side = xbar.slave
250 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
251 for tester, cache in zip(testers, tester_caches):
252 tester.port = cache.cpu_side
253 cache.mem_side = xbar.slave
254 else:
255 if not next_cache:
256 print "Error: No next-level cache at top level"
257 sys.exit(1)
258
259 if ntesters > 1:
260 # Create a crossbar and add it to the subsystem
261 xbar = L2XBar()
262 subsys.xbar = xbar
263 xbar.master = next_cache.cpu_side
264 for tester in testers:
265 tester.port = xbar.slave
266 else:
267 # Single tester
268 testers[0].port = next_cache.cpu_side
269
270# Top level call to create the cache hierarchy, bottom up
271make_cache_level(cachespec, cache_proto, len(cachespec), None)
272
273# Connect the lowest level crossbar to the memory
274last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
275last_subsys.xbar.master = system.physmem.port
276
277root = Root(full_system = False, system = system)
278if options.atomic:
279 root.system.mem_mode = 'atomic'
280else:
281 root.system.mem_mode = 'timing'
282
283# The system port is never used in the tester so merely connect it
284# to avoid problems
285root.system.system_port = last_subsys.xbar.slave
286
287# Instantiate configuration
288m5.instantiate()
289
290# Simulate until program terminates
291exit_event = m5.simulate(options.maxtick)
292
293print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
| 243 testers = [proto_tester(interval = 10 * (level * level + 1),
244 progress_check = limit) \
245 for i in xrange(ntesters)]
246 if ntesters:
247 subsys.tester = testers
248
249 if level != 0:
250 # Create a crossbar and add it to the subsystem, note that
251 # we do this even with a single element on this level
252 xbar = L2XBar()
253 subsys.xbar = xbar
254 if next_cache:
255 xbar.master = next_cache.cpu_side
256
257 # Create and connect the caches, both the ones fanning out
258 # to create the tree, and the ones used to connect testers
259 # on this level
260 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
261 tester_caches = [proto_l1() for i in xrange(ntesters)]
262
263 subsys.cache = tester_caches + tree_caches
264 for cache in tree_caches:
265 cache.mem_side = xbar.slave
266 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
267 for tester, cache in zip(testers, tester_caches):
268 tester.port = cache.cpu_side
269 cache.mem_side = xbar.slave
270 else:
271 if not next_cache:
272 print "Error: No next-level cache at top level"
273 sys.exit(1)
274
275 if ntesters > 1:
276 # Create a crossbar and add it to the subsystem
277 xbar = L2XBar()
278 subsys.xbar = xbar
279 xbar.master = next_cache.cpu_side
280 for tester in testers:
281 tester.port = xbar.slave
282 else:
283 # Single tester
284 testers[0].port = next_cache.cpu_side
285
286# Top level call to create the cache hierarchy, bottom up
287make_cache_level(cachespec, cache_proto, len(cachespec), None)
288
289# Connect the lowest level crossbar to the memory
290last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
291last_subsys.xbar.master = system.physmem.port
292
293root = Root(full_system = False, system = system)
294if options.atomic:
295 root.system.mem_mode = 'atomic'
296else:
297 root.system.mem_mode = 'timing'
298
299# The system port is never used in the tester so merely connect it
300# to avoid problems
301root.system.system_port = last_subsys.xbar.slave
302
303# Instantiate configuration
304m5.instantiate()
305
306# Simulate until program terminates
307exit_event = m5.simulate(options.maxtick)
308
309print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|