memtest.py (9793:6e6cefc1db1f) | memtest.py (9815:3b3b94536547) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 95 unchanged lines hidden (view full) --- 104 % (block_size) 105 sys.exit(1) 106 107if len(treespec) < 1: 108 print "Error parsing treespec" 109 sys.exit(1) 110 111# define prototype L1 cache | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 95 unchanged lines hidden (view full) --- 104 % (block_size) 105 sys.exit(1) 106 107if len(treespec) < 1: 108 print "Error parsing treespec" 109 sys.exit(1) 110 111# define prototype L1 cache |
112proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size, | 112proto_l1 = BaseCache(size = '32kB', assoc = 4, |
113 hit_latency = '1ns', response_latency = '1ns', 114 tgts_per_mshr = 8) 115 116if options.blocking: 117 proto_l1.mshrs = 1 118else: 119 proto_l1.mshrs = 4 120 --- 17 unchanged lines hidden (view full) --- 138 next.latency = prev.latency * 10 139 next.assoc = prev.assoc * scale 140 next.mshrs = prev.mshrs * scale 141 prototypes.insert(0, next) 142 143# system simulated 144system = System(funcmem = SimpleMemory(in_addr_map = False), 145 funcbus = NoncoherentBus(), | 113 hit_latency = '1ns', response_latency = '1ns', 114 tgts_per_mshr = 8) 115 116if options.blocking: 117 proto_l1.mshrs = 1 118else: 119 proto_l1.mshrs = 4 120 --- 17 unchanged lines hidden (view full) --- 138 next.latency = prev.latency * 10 139 next.assoc = prev.assoc * scale 140 next.mshrs = prev.mshrs * scale 141 prototypes.insert(0, next) 142 143# system simulated 144system = System(funcmem = SimpleMemory(in_addr_map = False), 145 funcbus = NoncoherentBus(), |
146 physmem = SimpleMemory(latency = "100ns")) | 146 physmem = SimpleMemory(latency = "100ns"), 147 cache_line_size = block_size) |
147system.clk_domain = SrcClockDomain(clock = options.sys_clock) 148 149def make_level(spec, prototypes, attach_obj, attach_port): 150 fanout = spec[0] 151 parent = attach_obj # use attach obj as config parent too 152 if len(spec) > 1 and (fanout > 1 or options.force_bus): 153 port = getattr(attach_obj, attach_port) 154 new_bus = CoherentBus(width=16) --- 51 unchanged lines hidden --- | 148system.clk_domain = SrcClockDomain(clock = options.sys_clock) 149 150def make_level(spec, prototypes, attach_obj, attach_port): 151 fanout = spec[0] 152 parent = attach_obj # use attach obj as config parent too 153 if len(spec) > 1 and (fanout > 1 or options.force_bus): 154 port = getattr(attach_obj, attach_port) 155 new_bus = CoherentBus(width=16) --- 51 unchanged lines hidden --- |