memtest.py (10405:7a618c07e663) | memtest.py (10688:22452667fd5c) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 110 unchanged lines hidden (view full) --- 119 120if options.blocking: 121 proto_l1.mshrs = 1 122else: 123 proto_l1.mshrs = 4 124 125# build a list of prototypes, one for each level of treespec, starting 126# at the end (last entry is tester objects) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 110 unchanged lines hidden (view full) --- 119 120if options.blocking: 121 proto_l1.mshrs = 1 122else: 123 proto_l1.mshrs = 4 124 125# build a list of prototypes, one for each level of treespec, starting 126# at the end (last entry is tester objects) |
127prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads, | 127prototypes = [ MemTest(max_loads=options.maxloads, |
128 percent_functional=options.functional, 129 percent_uncacheable=options.uncacheable, 130 progress_interval=options.progress) ] 131 132# next comes L1 cache, if any 133if len(treespec) > 1: 134 prototypes.insert(0, proto_l1) 135 --- 5 unchanged lines hidden (view full) --- 141 next.size = prev.size * scale 142 next.hit_latency = prev.hit_latency * 10 143 next.response_latency = prev.response_latency * 10 144 next.assoc = prev.assoc * scale 145 next.mshrs = prev.mshrs * scale 146 prototypes.insert(0, next) 147 148# system simulated | 128 percent_functional=options.functional, 129 percent_uncacheable=options.uncacheable, 130 progress_interval=options.progress) ] 131 132# next comes L1 cache, if any 133if len(treespec) > 1: 134 prototypes.insert(0, proto_l1) 135 --- 5 unchanged lines hidden (view full) --- 141 next.size = prev.size * scale 142 next.hit_latency = prev.hit_latency * 10 143 next.response_latency = prev.response_latency * 10 144 next.assoc = prev.assoc * scale 145 next.mshrs = prev.mshrs * scale 146 prototypes.insert(0, next) 147 148# system simulated |
149system = System(funcmem = SimpleMemory(in_addr_map = False), 150 funcbus = NoncoherentXBar(), 151 physmem = SimpleMemory(latency = "100ns"), | 149system = System(physmem = SimpleMemory(latency = "100ns"), |
152 cache_line_size = block_size) 153 | 150 cache_line_size = block_size) 151 |
154 | |
155system.voltage_domain = VoltageDomain(voltage = '1V') 156 157system.clk_domain = SrcClockDomain(clock = options.sys_clock, 158 voltage_domain = system.voltage_domain) 159 160def make_level(spec, prototypes, attach_obj, attach_port): 161 fanout = spec[0] 162 parent = attach_obj # use attach obj as config parent too --- 14 unchanged lines hidden (view full) --- 177 parent.cache = objs 178 for cache in objs: 179 cache.mem_side = getattr(attach_obj, attach_port) 180 make_level(spec[1:], prototypes[1:], cache, "cpu_side") 181 else: 182 # we just built the MemTest objects 183 parent.cpu = objs 184 for t in objs: | 152system.voltage_domain = VoltageDomain(voltage = '1V') 153 154system.clk_domain = SrcClockDomain(clock = options.sys_clock, 155 voltage_domain = system.voltage_domain) 156 157def make_level(spec, prototypes, attach_obj, attach_port): 158 fanout = spec[0] 159 parent = attach_obj # use attach obj as config parent too --- 14 unchanged lines hidden (view full) --- 174 parent.cache = objs 175 for cache in objs: 176 cache.mem_side = getattr(attach_obj, attach_port) 177 make_level(spec[1:], prototypes[1:], cache, "cpu_side") 178 else: 179 # we just built the MemTest objects 180 parent.cpu = objs 181 for t in objs: |
185 t.test = getattr(attach_obj, attach_port) 186 t.functional = system.funcbus.slave | 182 t.port = getattr(attach_obj, attach_port) |
187 188make_level(treespec, prototypes, system.physmem, "port") 189 | 183 184make_level(treespec, prototypes, system.physmem, "port") 185 |
190# connect reference memory to funcbus 191system.funcbus.master = system.funcmem.port 192 | |
193# ----------------------- 194# run simulation 195# ----------------------- 196 197root = Root( full_system = False, system = system ) 198if options.atomic: 199 root.system.mem_mode = 'atomic' 200else: 201 root.system.mem_mode = 'timing' 202 203# The system port is never used in the tester so merely connect it 204# to avoid problems | 186# ----------------------- 187# run simulation 188# ----------------------- 189 190root = Root( full_system = False, system = system ) 191if options.atomic: 192 root.system.mem_mode = 'atomic' 193else: 194 root.system.mem_mode = 'timing' 195 196# The system port is never used in the tester so merely connect it 197# to avoid problems |
205root.system.system_port = root.system.funcbus.slave | 198root.system.system_port = root.system.physmem.cpu_side_bus.slave |
206 207# Not much point in this being higher than the L1 latency 208m5.ticks.setGlobalFrequency('1ns') 209 210# instantiate configuration 211m5.instantiate() 212 213# simulate until program terminates 214exit_event = m5.simulate(options.maxtick) 215 216print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() | 199 200# Not much point in this being higher than the L1 latency 201m5.ticks.setGlobalFrequency('1ns') 202 203# instantiate configuration 204m5.instantiate() 205 206# simulate until program terminates 207exit_event = m5.simulate(options.maxtick) 208 209print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() |