fs.py (9826:014ff1fbff6d) fs.py (9827:f47274776aa0)
1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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111 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
112elif buildEnv['TARGET_ISA'] == "arm":
113 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
114 options.dtb_filename,
115 bare_metal=options.bare_metal)
116else:
117 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
118
1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 102 unchanged lines hidden (view full) ---

111 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
112elif buildEnv['TARGET_ISA'] == "arm":
113 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
114 options.dtb_filename,
115 bare_metal=options.bare_metal)
116else:
117 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
118
119# Create a top-level voltage domain
120test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
121
119# Create a source clock for the system and set the clock period
122# Create a source clock for the system and set the clock period
120test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
123test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
124 voltage_domain = test_sys.voltage_domain)
121
125
126# Create a CPU voltage domain
127test_sys.cpu_voltage_domain = VoltageDomain()
128
122# Create a source clock for the CPUs and set the clock period
129# Create a source clock for the CPUs and set the clock period
123test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
130test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
131 voltage_domain =
132 test_sys.cpu_voltage_domain)
124
125if options.kernel is not None:
126 test_sys.kernel = binary(options.kernel)
127
128if options.script is not None:
129 test_sys.readfile = options.script
130
131test_sys.init_param = options.init_param

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177 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
178 elif buildEnv['TARGET_ISA'] == 'sparc':
179 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
180 elif buildEnv['TARGET_ISA'] == 'x86':
181 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
182 elif buildEnv['TARGET_ISA'] == 'arm':
183 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
184
133
134if options.kernel is not None:
135 test_sys.kernel = binary(options.kernel)
136
137if options.script is not None:
138 test_sys.readfile = options.script
139
140test_sys.init_param = options.init_param

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186 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
187 elif buildEnv['TARGET_ISA'] == 'sparc':
188 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
189 elif buildEnv['TARGET_ISA'] == 'x86':
190 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
191 elif buildEnv['TARGET_ISA'] == 'arm':
192 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
193
194 # Create a top-level voltage domain
195 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
196
185 # Create a source clock for the system and set the clock period
186 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
187
197 # Create a source clock for the system and set the clock period
198 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
199
200 # Create a CPU voltage domain
201 drive_sys.cpu_voltage_domain = VoltageDomain()
202
188 # Create a source clock for the CPUs and set the clock period
203 # Create a source clock for the CPUs and set the clock period
189 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
204 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
205 voltage_domain =
206 drive_sys.cpu_voltage_domain)
190
191 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
192 cpu_id=0)
193 drive_sys.cpu.createThreads()
194 drive_sys.cpu.createInterruptController()
195 drive_sys.cpu.connectAllPorts(drive_sys.membus)
196 if options.fastmem:
197 drive_sys.cpu.fastmem = True

--- 34 unchanged lines hidden --- 		207
208 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
209 cpu_id=0)
210 drive_sys.cpu.createThreads()
211 drive_sys.cpu.createInterruptController()
212 drive_sys.cpu.connectAllPorts(drive_sys.membus)
213 if options.fastmem:
214 drive_sys.cpu.fastmem = True

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