| fs.py (9665:6dbdeee787cc) | fs.py (9788:5558ee8dd7d9) |
|---|---|
| 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 120 unchanged lines hidden (view full) --- 129test_sys.init_param = options.init_param 130 131test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 132 133if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 134 test_sys.vm = KvmVM() 135 136if options.caches or options.l2cache: | 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 120 unchanged lines hidden (view full) --- 129test_sys.init_param = options.init_param 130 131test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 132 133if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 134 test_sys.vm = KvmVM() 135 136if options.caches or options.l2cache: |
| 137 test_sys.iocache = IOCache(clock = '1GHz', 138 addr_ranges = test_sys.mem_ranges) | 137 # By default the IOCache runs at the system clock 138 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) |
| 139 test_sys.iocache.cpu_side = test_sys.iobus.master 140 test_sys.iocache.mem_side = test_sys.membus.slave 141else: 142 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 143 test_sys.iobridge.slave = test_sys.iobus.master 144 test_sys.iobridge.master = test_sys.membus.slave 145 146# Sanity check --- 61 unchanged lines hidden --- | 139 test_sys.iocache.cpu_side = test_sys.iobus.master 140 test_sys.iocache.mem_side = test_sys.membus.slave 141else: 142 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 143 test_sys.iobridge.slave = test_sys.iobus.master 144 test_sys.iobridge.master = test_sys.membus.slave 145 146# Sanity check --- 61 unchanged lines hidden --- |