fs.py (9384:877293183bdf) fs.py (9408:10a84dceab25)
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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114 test_sys.readfile = options.script
115
116test_sys.init_param = options.init_param
117
118test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
119
120if options.caches or options.l2cache:
121 test_sys.iocache = IOCache(clock = '1GHz',
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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114 test_sys.readfile = options.script
115
116test_sys.init_param = options.init_param
117
118test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
119
120if options.caches or options.l2cache:
121 test_sys.iocache = IOCache(clock = '1GHz',
122 addr_ranges=[test_sys.physmem.range])
122 addr_ranges = test_sys.mem_ranges)
123 test_sys.iocache.cpu_side = test_sys.iobus.master
124 test_sys.iocache.mem_side = test_sys.membus.slave
125else:
123 test_sys.iocache.cpu_side = test_sys.iobus.master
124 test_sys.iocache.mem_side = test_sys.membus.slave
125else:
126 test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range])
126 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
127 test_sys.iobridge.slave = test_sys.iobus.master
128 test_sys.iobridge.master = test_sys.membus.slave
129
130# Sanity check
131if options.fastmem:
132 if TestCPUClass != AtomicSimpleCPU:
133 fatal("Fastmem can only be used with atomic CPU!")
134 if (options.caches or options.l2cache):

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158 drive_sys.cpu = DriveCPUClass(cpu_id=0)
159 drive_sys.cpu.createThreads()
160 drive_sys.cpu.createInterruptController()
161 drive_sys.cpu.connectAllPorts(drive_sys.membus)
162 if options.fastmem:
163 drive_sys.cpu.fastmem = True
164 if options.kernel is not None:
165 drive_sys.kernel = binary(options.kernel)
127 test_sys.iobridge.slave = test_sys.iobus.master
128 test_sys.iobridge.master = test_sys.membus.slave
129
130# Sanity check
131if options.fastmem:
132 if TestCPUClass != AtomicSimpleCPU:
133 fatal("Fastmem can only be used with atomic CPU!")
134 if (options.caches or options.l2cache):

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158 drive_sys.cpu = DriveCPUClass(cpu_id=0)
159 drive_sys.cpu.createThreads()
160 drive_sys.cpu.createInterruptController()
161 drive_sys.cpu.connectAllPorts(drive_sys.membus)
162 if options.fastmem:
163 drive_sys.cpu.fastmem = True
164 if options.kernel is not None:
165 drive_sys.kernel = binary(options.kernel)
166
166 drive_sys.iobridge = Bridge(delay='50ns',
167 drive_sys.iobridge = Bridge(delay='50ns',
167 ranges = [drive_sys.physmem.range])
168 ranges = drive_sys.mem_ranges)
168 drive_sys.iobridge.slave = drive_sys.iobus.master
169 drive_sys.iobridge.master = drive_sys.membus.slave
170
171 drive_sys.init_param = options.init_param
172 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
173elif len(bm) == 1:
174 root = Root(full_system=True, system=test_sys)
175else:
176 print "Error I don't know how to create more than 2 systems."
177 sys.exit(1)
178
179if options.timesync:
180 root.time_sync_enable = True
181
182if options.frame_capture:
183 VncServer.frame_capture = True
184
185Simulation.setWorkCountOptions(test_sys, options)
186Simulation.run(options, root, test_sys, FutureClass)
169 drive_sys.iobridge.slave = drive_sys.iobus.master
170 drive_sys.iobridge.master = drive_sys.membus.slave
171
172 drive_sys.init_param = options.init_param
173 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
174elif len(bm) == 1:
175 root = Root(full_system=True, system=test_sys)
176else:
177 print "Error I don't know how to create more than 2 systems."
178 sys.exit(1)
179
180if options.timesync:
181 root.time_sync_enable = True
182
183if options.frame_capture:
184 VncServer.frame_capture = True
185
186Simulation.setWorkCountOptions(test_sys, options)
187Simulation.run(options, root, test_sys, FutureClass)