| fs.py (8887:20ea02da9c53) | fs.py (8894:351585c17699) |
|---|---|
| 1# Copyright (c) 2010-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 143 unchanged lines hidden (view full) --- 152 153test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 154 155if bm[0]: 156 mem_size = bm[0].mem() 157else: 158 mem_size = SysConfig().mem() 159if options.caches or options.l2cache: | 1# Copyright (c) 2010-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 143 unchanged lines hidden (view full) --- 152 153test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 154 155if bm[0]: 156 mem_size = bm[0].mem() 157else: 158 mem_size = SysConfig().mem() 159if options.caches or options.l2cache: |
| 160 test_sys.iocache = IOCache(addr_ranges=[mem_size]) | 160 test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range]) |
| 161 test_sys.iocache.cpu_side = test_sys.iobus.master 162 test_sys.iocache.mem_side = test_sys.membus.slave 163else: 164 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 165 ranges = [test_sys.physmem.range]) 166 test_sys.iobridge.slave = test_sys.iobus.master 167 test_sys.iobridge.master = test_sys.membus.slave 168 --- 50 unchanged lines hidden --- | 161 test_sys.iocache.cpu_side = test_sys.iobus.master 162 test_sys.iocache.mem_side = test_sys.membus.slave 163else: 164 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 165 ranges = [test_sys.physmem.range]) 166 test_sys.iobridge.slave = test_sys.iobus.master 167 test_sys.iobridge.master = test_sys.membus.slave 168 --- 50 unchanged lines hidden --- |