fs.py (8883:c92153af04ac) fs.py (8887:20ea02da9c53)
1# Copyright (c) 2010-2011 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 138 unchanged lines hidden (view full) ---

147
148if options.script is not None:
149 test_sys.readfile = options.script
150
151test_sys.init_param = options.init_param
152
153test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
154
1# Copyright (c) 2010-2011 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 138 unchanged lines hidden (view full) ---

147
148if options.script is not None:
149 test_sys.readfile = options.script
150
151test_sys.init_param = options.init_param
152
153test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
154
155CacheConfig.config_cache(options, test_sys)
156
157if bm[0]:
158 mem_size = bm[0].mem()
159else:
160 mem_size = SysConfig().mem()
161if options.caches or options.l2cache:
162 test_sys.iocache = IOCache(addr_ranges=[mem_size])
163 test_sys.iocache.cpu_side = test_sys.iobus.master
164 test_sys.iocache.mem_side = test_sys.membus.slave
165else:
166 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
167 ranges = [test_sys.physmem.range])
168 test_sys.iobridge.slave = test_sys.iobus.master
169 test_sys.iobridge.master = test_sys.membus.slave
170
171for i in xrange(np):
172 if options.fastmem:
173 test_sys.cpu[i].physmem_port = test_sys.physmem.port
155if bm[0]:
156 mem_size = bm[0].mem()
157else:
158 mem_size = SysConfig().mem()
159if options.caches or options.l2cache:
160 test_sys.iocache = IOCache(addr_ranges=[mem_size])
161 test_sys.iocache.cpu_side = test_sys.iobus.master
162 test_sys.iocache.mem_side = test_sys.membus.slave
163else:
164 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
165 ranges = [test_sys.physmem.range])
166 test_sys.iobridge.slave = test_sys.iobus.master
167 test_sys.iobridge.master = test_sys.membus.slave
168
169for i in xrange(np):
170 if options.fastmem:
171 test_sys.cpu[i].physmem_port = test_sys.physmem.port
172 if options.checker:
173 test_sys.cpu[i].addCheckerCpu()
174
174
175CacheConfig.config_cache(options, test_sys)
176
175if buildEnv['TARGET_ISA'] == 'mips':
176 setMipsOptions(TestCPUClass)
177
178if len(bm) == 2:
179 if buildEnv['TARGET_ISA'] == 'alpha':
180 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
181 elif buildEnv['TARGET_ISA'] == 'mips':
182 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])

--- 34 unchanged lines hidden --- 		177if buildEnv['TARGET_ISA'] == 'mips':
178 setMipsOptions(TestCPUClass)
179
180if len(bm) == 2:
181 if buildEnv['TARGET_ISA'] == 'alpha':
182 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
183 elif buildEnv['TARGET_ISA'] == 'mips':
184 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])

--- 34 unchanged lines hidden ---