| fs.py (8870:f95c4042f2d0) | fs.py (8883:c92153af04ac) |
|---|---|
| 1# Copyright (c) 2010-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154 155CacheConfig.config_cache(options, test_sys) 156 157if bm[0]: 158 mem_size = bm[0].mem() 159else: 160 mem_size = SysConfig().mem() 161if options.caches or options.l2cache: | 1# Copyright (c) 2010-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154 155CacheConfig.config_cache(options, test_sys) 156 157if bm[0]: 158 mem_size = bm[0].mem() 159else: 160 mem_size = SysConfig().mem() 161if options.caches or options.l2cache: |
| 162 test_sys.iocache = IOCache(addr_range=test_sys.physmem.range) | 162 test_sys.iocache = IOCache(addr_ranges=[mem_size]) |
| 163 test_sys.iocache.cpu_side = test_sys.iobus.master 164 test_sys.iocache.mem_side = test_sys.membus.slave 165else: 166 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 167 ranges = [test_sys.physmem.range]) 168 test_sys.iobridge.slave = test_sys.iobus.master 169 test_sys.iobridge.master = test_sys.membus.slave 170 --- 46 unchanged lines hidden --- | 163 test_sys.iocache.cpu_side = test_sys.iobus.master 164 test_sys.iocache.mem_side = test_sys.membus.slave 165else: 166 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 167 ranges = [test_sys.physmem.range]) 168 test_sys.iobridge.slave = test_sys.iobus.master 169 test_sys.iobridge.master = test_sys.membus.slave 170 --- 46 unchanged lines hidden --- |