Cross Reference: /gem5/configs/example/fs.py

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fs.py (8863:50ce4deacda9)	fs.py (8870:f95c4042f2d0)
1# Copyright (c) 2010-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154 155CacheConfig.config_cache(options, test_sys) 156 157if bm[0]: 158 mem_size = bm[0].mem() 159else: 160 mem_size = SysConfig().mem() 161if options.caches or options.l2cache:	1# Copyright (c) 2010-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 145 unchanged lines hidden (view full) --- 154 155CacheConfig.config_cache(options, test_sys) 156 157if bm[0]: 158 mem_size = bm[0].mem() 159else: 160 mem_size = SysConfig().mem() 161if options.caches or options.l2cache:
162 test_sys.iocache = IOCache(addr_range=mem_size)	162 test_sys.iocache = IOCache(addr_range=test_sys.physmem.range)
163 test_sys.iocache.cpu_side = test_sys.iobus.master 164 test_sys.iocache.mem_side = test_sys.membus.slave 165else: 166 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',	163 test_sys.iocache.cpu_side = test_sys.iobus.master 164 test_sys.iocache.mem_side = test_sys.membus.slave 165else: 166 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
167 ranges = [AddrRange(mem_size)])	167 ranges = [test_sys.physmem.range])
168 test_sys.iobridge.slave = test_sys.iobus.master 169 test_sys.iobridge.master = test_sys.membus.slave 170 171for i in xrange(np): 172 if options.fastmem: 173 test_sys.cpu[i].physmem_port = test_sys.physmem.port 174 175if buildEnv['TARGET_ISA'] == 'mips': --- 14 unchanged lines hidden (view full) --- 190 drive_sys.cpu = DriveCPUClass(cpu_id=0) 191 drive_sys.cpu.createInterruptController() 192 drive_sys.cpu.connectAllPorts(drive_sys.membus) 193 if options.fastmem: 194 drive_sys.cpu.physmem_port = drive_sys.physmem.port 195 if options.kernel is not None: 196 drive_sys.kernel = binary(options.kernel) 197 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',	168 test_sys.iobridge.slave = test_sys.iobus.master 169 test_sys.iobridge.master = test_sys.membus.slave 170 171for i in xrange(np): 172 if options.fastmem: 173 test_sys.cpu[i].physmem_port = test_sys.physmem.port 174 175if buildEnv['TARGET_ISA'] == 'mips': --- 14 unchanged lines hidden (view full) --- 190 drive_sys.cpu = DriveCPUClass(cpu_id=0) 191 drive_sys.cpu.createInterruptController() 192 drive_sys.cpu.connectAllPorts(drive_sys.membus) 193 if options.fastmem: 194 drive_sys.cpu.physmem_port = drive_sys.physmem.port 195 if options.kernel is not None: 196 drive_sys.kernel = binary(options.kernel) 197 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
198 ranges = [AddrRange(bm[1].mem())])	198 ranges = [drive_sys.physmem.range])
199 drive_sys.iobridge.slave = drive_sys.iobus.master 200 drive_sys.iobridge.master = drive_sys.membus.slave 201 202 drive_sys.init_param = options.init_param 203 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 204elif len(bm) == 1: 205 root = Root(full_system=True, system=test_sys) 206else: 207 print "Error I don't know how to create more than 2 systems." 208 sys.exit(1) 209 210if options.timesync: 211 root.time_sync_enable = True 212 213if options.frame_capture: 214 VncServer.frame_capture = True 215 216Simulation.run(options, root, test_sys, FutureClass)	199 drive_sys.iobridge.slave = drive_sys.iobus.master 200 drive_sys.iobridge.master = drive_sys.membus.slave 201 202 drive_sys.init_param = options.init_param 203 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 204elif len(bm) == 1: 205 root = Root(full_system=True, system=test_sys) 206else: 207 print "Error I don't know how to create more than 2 systems." 208 sys.exit(1) 209 210if options.timesync: 211 root.time_sync_enable = True 212 213if options.frame_capture: 214 VncServer.frame_capture = True 215 216Simulation.run(options, root, test_sys, FutureClass)