fs.py (8845:a230379caf65) fs.py (8863:50ce4deacda9)
1# Copyright (c) 2010-2011 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 174 unchanged lines hidden (view full) ---

183 elif buildEnv['TARGET_ISA'] == 'sparc':
184 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
185 elif buildEnv['TARGET_ISA'] == 'x86':
186 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
187 elif buildEnv['TARGET_ISA'] == 'arm':
188 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
189
190 drive_sys.cpu = DriveCPUClass(cpu_id=0)
1# Copyright (c) 2010-2011 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 174 unchanged lines hidden (view full) ---

183 elif buildEnv['TARGET_ISA'] == 'sparc':
184 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
185 elif buildEnv['TARGET_ISA'] == 'x86':
186 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
187 elif buildEnv['TARGET_ISA'] == 'arm':
188 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
189
190 drive_sys.cpu = DriveCPUClass(cpu_id=0)
191 drive_sys.cpu.createInterruptController()
191 drive_sys.cpu.connectAllPorts(drive_sys.membus)
192 if options.fastmem:
193 drive_sys.cpu.physmem_port = drive_sys.physmem.port
194 if options.kernel is not None:
195 drive_sys.kernel = binary(options.kernel)
196 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
197 ranges = [AddrRange(bm[1].mem())])
198 drive_sys.iobridge.slave = drive_sys.iobus.master

--- 17 unchanged lines hidden --- 		192 drive_sys.cpu.connectAllPorts(drive_sys.membus)
193 if options.fastmem:
194 drive_sys.cpu.physmem_port = drive_sys.physmem.port
195 if options.kernel is not None:
196 drive_sys.kernel = binary(options.kernel)
197 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
198 ranges = [AddrRange(bm[1].mem())])
199 drive_sys.iobridge.slave = drive_sys.iobus.master

--- 17 unchanged lines hidden ---