| fs.py (8713:2f1a3e335255) | fs.py (8723:bbcc7afd82cb) |
|---|---|
| 1# Copyright (c) 2010-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 153 unchanged lines hidden (view full) --- 162else: 163 mem_size = SysConfig().mem() 164if options.caches or options.l2cache: 165 test_sys.iocache = IOCache(addr_range=mem_size) 166 test_sys.iocache.cpu_side = test_sys.iobus.port 167 test_sys.iocache.mem_side = test_sys.membus.port 168else: 169 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', | 1# Copyright (c) 2010-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 153 unchanged lines hidden (view full) --- 162else: 163 mem_size = SysConfig().mem() 164if options.caches or options.l2cache: 165 test_sys.iocache = IOCache(addr_range=mem_size) 166 test_sys.iocache.cpu_side = test_sys.iobus.port 167 test_sys.iocache.mem_side = test_sys.membus.port 168else: 169 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', |
| 170 ranges = [AddrRange(0, mem_size)]) | 170 ranges = [AddrRange(mem_size)]) |
| 171 test_sys.iobridge.slave = test_sys.iobus.port 172 test_sys.iobridge.master = test_sys.membus.port 173 174for i in xrange(np): 175 if options.fastmem: 176 test_sys.cpu[i].physmem_port = test_sys.physmem.port 177 178if buildEnv['TARGET_ISA'] == 'mips': --- 36 unchanged lines hidden --- | 171 test_sys.iobridge.slave = test_sys.iobus.port 172 test_sys.iobridge.master = test_sys.membus.port 173 174for i in xrange(np): 175 if options.fastmem: 176 test_sys.cpu[i].physmem_port = test_sys.physmem.port 177 178if buildEnv['TARGET_ISA'] == 'mips': --- 36 unchanged lines hidden --- |