fs.py (7876:189b9b258779) fs.py (7877:19beb0676222)
1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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148
149CacheConfig.config_cache(options, test_sys)
150
151if options.caches or options.l2cache:
152 if bm[0]:
153 mem_size = bm[0].mem()
154 else:
155 mem_size = SysConfig().mem()
1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 139 unchanged lines hidden (view full) ---

148
149CacheConfig.config_cache(options, test_sys)
150
151if options.caches or options.l2cache:
152 if bm[0]:
153 mem_size = bm[0].mem()
154 else:
155 mem_size = SysConfig().mem()
156 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
156 # For x86, we need to poke a hole for interrupt messages to get back to the
157 # CPU. These use a portion of the physical address space which has a
158 # non-zero prefix in the top nibble. Normal memory accesses have a 0
159 # prefix.
160 if buildEnv['TARGET_ISA'] == 'x86':
161 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)]
162 else:
163 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
157 test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
158 test_sys.iocache = IOCache(addr_range=mem_size)
159 test_sys.iocache.cpu_side = test_sys.iobus.port
160 test_sys.iocache.mem_side = test_sys.membus.port
161
162for i in xrange(np):
163 if options.fastmem:
164 test_sys.cpu[i].physmem_port = test_sys.physmem.port

--- 33 unchanged lines hidden --- 		164 test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
165 test_sys.iocache = IOCache(addr_range=mem_size)
166 test_sys.iocache.cpu_side = test_sys.iobus.port
167 test_sys.iocache.mem_side = test_sys.membus.port
168
169for i in xrange(np):
170 if options.fastmem:
171 test_sys.cpu[i].physmem_port = test_sys.physmem.port

--- 33 unchanged lines hidden ---