fs.py (5822:05ffa2c3c800) fs.py (6122:9af6fb59752f)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 112 unchanged lines hidden (view full) ---

121 test_sys.l2.cpu_side = test_sys.tol2bus.port
122 test_sys.l2.mem_side = test_sys.membus.port
123
124test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
125
126if options.caches:
127 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
128 test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 112 unchanged lines hidden (view full) ---

121 test_sys.l2.cpu_side = test_sys.tol2bus.port
122 test_sys.l2.mem_side = test_sys.membus.port
123
124test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
125
126if options.caches:
127 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
128 test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
129 test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
130 cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
129 test_sys.iocache = IOCache(addr_range=AddrRange(0, size='8GB'))
131 test_sys.iocache.cpu_side = test_sys.iobus.port
132 test_sys.iocache.mem_side = test_sys.membus.port
133
134for i in xrange(np):
135 if options.caches:
136 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
137 L1Cache(size = '64kB'))
138 if options.l2cache:

--- 34 unchanged lines hidden --- 		130 test_sys.iocache.cpu_side = test_sys.iobus.port
131 test_sys.iocache.mem_side = test_sys.membus.port
132
133for i in xrange(np):
134 if options.caches:
135 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
136 L1Cache(size = '64kB'))
137 if options.l2cache:

--- 34 unchanged lines hidden ---