Cross Reference: /gem5/configs/example/fs.py

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fs.py (5142:73aa4932b65b)	fs.py (5222:bb733a878f85)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 83 unchanged lines hidden (view full) --- 92else: 93 if options.dual: 94 bm = [SysConfig(), SysConfig()] 95 else: 96 bm = [SysConfig()] 97 98if m5.build_env['TARGET_ISA'] == "alpha": 99 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])	1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 83 unchanged lines hidden (view full) --- 92else: 93 if options.dual: 94 bm = [SysConfig(), SysConfig()] 95 else: 96 bm = [SysConfig()] 97 98if m5.build_env['TARGET_ISA'] == "alpha": 99 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
	100elif m5.build_env['TARGET_ISA'] == "mips": 101 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
100elif m5.build_env['TARGET_ISA'] == "sparc": 101 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 102elif m5.build_env['TARGET_ISA'] == "x86": 103 test_sys = makeX86System(test_mem_mode, bm[0]) 104else: 105 m5.panic("incapable of building non-alpha or non-sparc full system!") 106 107if options.kernel is not None: --- 27 unchanged lines hidden (view full) --- 135 if options.l2cache: 136 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus) 137 else: 138 test_sys.cpu[i].connectMemPorts(test_sys.membus) 139 140 if options.fastmem: 141 test_sys.cpu[i].physmem_port = test_sys.physmem.port 142	102elif m5.build_env['TARGET_ISA'] == "sparc": 103 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 104elif m5.build_env['TARGET_ISA'] == "x86": 105 test_sys = makeX86System(test_mem_mode, bm[0]) 106else: 107 m5.panic("incapable of building non-alpha or non-sparc full system!") 108 109if options.kernel is not None: --- 27 unchanged lines hidden (view full) --- 137 if options.l2cache: 138 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus) 139 else: 140 test_sys.cpu[i].connectMemPorts(test_sys.membus) 141 142 if options.fastmem: 143 test_sys.cpu[i].physmem_port = test_sys.physmem.port 144
	145if m5.build_env['TARGET_ISA'] == 'mips': 146 #CP0 Configuration 147 TestCPUClass.CP0_PRId_CompanyOptions = 0 148 TestCPUClass.CP0_PRId_CompanyID = 1 149 TestCPUClass.CP0_PRId_ProcessorID = 147 150 TestCPUClass.CP0_PRId_Revision = 0 151 152 #CP0 Interrupt Control 153 TestCPUClass.CP0_IntCtl_IPTI = 7 154 TestCPUClass.CP0_IntCtl_IPPCI = 7 155 156 # Config Register 157 #TestCPUClass.CP0_Config_K23 = 0 # Since TLB 158 #TestCPUClass.CP0_Config_KU = 0 # Since TLB 159 TestCPUClass.CP0_Config_BE = 0 # Little Endian 160 TestCPUClass.CP0_Config_AR = 1 # Architecture Revision 2 161 TestCPUClass.CP0_Config_AT = 0 # MIPS32 162 TestCPUClass.CP0_Config_MT = 1 # TLB MMU 163 #TestCPUClass.CP0_Config_K0 = 2 # Uncached 164 165 #Config 1 Register 166 TestCPUClass.CP0_Config1_M = 1 # Config2 Implemented 167 TestCPUClass.CP0_Config1_MMU = 63 # TLB Size 168 # *VERY IMPORTANT* 169 # Remember to modify CP0_Config1 according to cache specs 170 # Examine file ../common/Cache.py 171 TestCPUClass.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 172 TestCPUClass.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 173 TestCPUClass.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 174 TestCPUClass.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 175 TestCPUClass.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 176 TestCPUClass.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 177 TestCPUClass.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 178 TestCPUClass.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 179 TestCPUClass.CP0_Config1_PC = 1 # Performance Counters Implemented 180 TestCPUClass.CP0_Config1_WR = 0 # Watch Registers Implemented 181 TestCPUClass.CP0_Config1_CA = 0 # Mips16e NOT implemented 182 TestCPUClass.CP0_Config1_EP = 0 # EJTag Not Implemented 183 TestCPUClass.CP0_Config1_FP = 0 # FPU Implemented 184 185 #Config 2 Register 186 TestCPUClass.CP0_Config2_M = 1 # Config3 Implemented 187 TestCPUClass.CP0_Config2_TU = 0 # Tertiary Cache Control 188 TestCPUClass.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 189 TestCPUClass.CP0_Config2_TL = 0 # Tertiary Cache Line Size 190 TestCPUClass.CP0_Config2_TA = 0 # Tertiary Cache Associativity 191 TestCPUClass.CP0_Config2_SU = 0 # Secondary Cache Control 192 TestCPUClass.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 193 TestCPUClass.CP0_Config2_SL = 0 # Secondary Cache Line Size 194 TestCPUClass.CP0_Config2_SA = 0 # Secondary Cache Associativity 195 196 197 #Config 3 Register 198 TestCPUClass.CP0_Config3_M = 0 # Config4 Not Implemented 199 TestCPUClass.CP0_Config3_DSPP = 1 # DSP ASE Present 200 TestCPUClass.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 201 TestCPUClass.CP0_Config3_VEIC = 0 # EIC Supported 202 TestCPUClass.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 203 TestCPUClass.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 204 TestCPUClass.CP0_Config3_MT = 0 # MT Not present 205 TestCPUClass.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 206 TestCPUClass.CP0_Config3_TL = 0 # TraceLogic Not implemented 207 208 #SRS Ctl - HSS 209 TestCPUClass.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 210 211 212 #TestCPUClass.tlb = TLB() 213 #TestCPUClass.UnifiedTLB = 1 214
143if len(bm) == 2: 144 if m5.build_env['TARGET_ISA'] == 'alpha': 145 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])	215if len(bm) == 2: 216 if m5.build_env['TARGET_ISA'] == 'alpha': 217 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
	218 elif m5.build_env['TARGET_ISA'] == 'mips': 219 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
146 elif m5.build_env['TARGET_ISA'] == 'sparc': 147 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 148 elif m5.build.env['TARGET_ISA'] == 'x86': 149 drive_sys = makeX86System(drive_mem_mode, bm[1]) 150 drive_sys.cpu = DriveCPUClass(cpu_id=0) 151 drive_sys.cpu.connectMemPorts(drive_sys.membus) 152 if options.fastmem: 153 drive_sys.cpu.physmem_port = drive_sys.physmem.port 154 if options.kernel is not None: 155 drive_sys.kernel = binary(options.kernel) 156 157 root = makeDualRoot(test_sys, drive_sys, options.etherdump) 158elif len(bm) == 1: 159 root = Root(system=test_sys) 160else: 161 print "Error I don't know how to create more than 2 systems." 162 sys.exit(1) 163 164Simulation.run(options, root, test_sys, FutureClass)	220 elif m5.build_env['TARGET_ISA'] == 'sparc': 221 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 222 elif m5.build.env['TARGET_ISA'] == 'x86': 223 drive_sys = makeX86System(drive_mem_mode, bm[1]) 224 drive_sys.cpu = DriveCPUClass(cpu_id=0) 225 drive_sys.cpu.connectMemPorts(drive_sys.membus) 226 if options.fastmem: 227 drive_sys.cpu.physmem_port = drive_sys.physmem.port 228 if options.kernel is not None: 229 drive_sys.kernel = binary(options.kernel) 230 231 root = makeDualRoot(test_sys, drive_sys, options.etherdump) 232elif len(bm) == 1: 233 root = Root(system=test_sys) 234else: 235 print "Error I don't know how to create more than 2 systems." 236 sys.exit(1) 237 238Simulation.run(options, root, test_sys, FutureClass)