fs.py (5133:a88763dd4a84) fs.py (5142:73aa4932b65b)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 105 unchanged lines hidden (view full) ---

114
115if options.l2cache:
116 test_sys.l2 = L2Cache(size = '2MB')
117 test_sys.tol2bus = Bus()
118 test_sys.l2.cpu_side = test_sys.tol2bus.port
119 test_sys.l2.mem_side = test_sys.membus.port
120
121test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 105 unchanged lines hidden (view full) ---

114
115if options.l2cache:
116 test_sys.l2 = L2Cache(size = '2MB')
117 test_sys.tol2bus = Bus()
118 test_sys.l2.cpu_side = test_sys.tol2bus.port
119 test_sys.l2.mem_side = test_sys.membus.port
120
121test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
122
123if options.caches:
124 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
125 test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
126 test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
127 cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
128 test_sys.iocache.cpu_side = test_sys.iobus.port
129 test_sys.iocache.mem_side = test_sys.membus.port
130
122for i in xrange(np):
123 if options.caches:
124 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
125 L1Cache(size = '64kB'))
131for i in xrange(np):
132 if options.caches:
133 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
134 L1Cache(size = '64kB'))
126 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
127 test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
128 test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
129 cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
130 test_sys.iocache.cpu_side = test_sys.iobus.port
131 test_sys.iocache.mem_side = test_sys.membus.port
132 if options.l2cache:
133 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
134 else:
135 test_sys.cpu[i].connectMemPorts(test_sys.membus)
136
137 if options.fastmem:
138 test_sys.cpu[i].physmem_port = test_sys.physmem.port
139

--- 22 unchanged lines hidden --- 		135 if options.l2cache:
136 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
137 else:
138 test_sys.cpu[i].connectMemPorts(test_sys.membus)
139
140 if options.fastmem:
141 test_sys.cpu[i].physmem_port = test_sys.physmem.port
142

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