fs.py (4837:4e5c7f774548) fs.py (4965:ad0e792a5c78)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 107 unchanged lines hidden (view full) ---

116 test_sys.l2.cpu_side = test_sys.tol2bus.port
117 test_sys.l2.mem_side = test_sys.membus.port
118
119test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
120for i in xrange(np):
121 if options.caches:
122 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
123 L1Cache(size = '64kB'))
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 107 unchanged lines hidden (view full) ---

116 test_sys.l2.cpu_side = test_sys.tol2bus.port
117 test_sys.l2.mem_side = test_sys.membus.port
118
119test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
120for i in xrange(np):
121 if options.caches:
122 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
123 L1Cache(size = '64kB'))
124
124 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
125 test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
126 test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
127 cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
128 test_sys.iocache.cpu_side = test_sys.iobus.port
129 test_sys.iocache.mem_side = test_sys.membus.port
125 if options.l2cache:
126 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
127 else:
128 test_sys.cpu[i].connectMemPorts(test_sys.membus)
129
130if len(bm) == 2:
131 if m5.build_env['TARGET_ISA'] == 'alpha':
132 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])

--- 15 unchanged lines hidden --- 		130 if options.l2cache:
131 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
132 else:
133 test_sys.cpu[i].connectMemPorts(test_sys.membus)
134
135if len(bm) == 2:
136 if m5.build_env['TARGET_ISA'] == 'alpha':
137 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])

--- 15 unchanged lines hidden ---