fs.py (3668:bacb0a392e78) | fs.py (3819:8a9d3f3d3398) |
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1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 78 unchanged lines hidden (view full) --- 87 print "Valid benchmarks are: %s" % DefinedBenchmarks 88 sys.exit(1) 89else: 90 if options.dual: 91 bm = [SysConfig(), SysConfig()] 92 else: 93 bm = [SysConfig()] 94 | 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 78 unchanged lines hidden (view full) --- 87 print "Valid benchmarks are: %s" % DefinedBenchmarks 88 sys.exit(1) 89else: 90 if options.dual: 91 bm = [SysConfig(), SysConfig()] 92 else: 93 bm = [SysConfig()] 94 |
95test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) | 95if m5.build_env['TARGET_ISA'] == "alpha": 96 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 97elif m5.build_env['TARGET_ISA'] == "sparc": 98 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 99else: 100 m5.panic("incapable of building non-alpha or non-sparc full system!") 101 |
96np = options.num_cpus 97 98if options.l2cache: 99 test_sys.l2 = L2Cache(size = '2MB') 100 test_sys.tol2bus = Bus() 101 test_sys.l2.cpu_side = test_sys.tol2bus.port 102 test_sys.l2.mem_side = test_sys.membus.port 103 --- 4 unchanged lines hidden (view full) --- 108 L1Cache(size = '64kB')) 109 110 if options.l2cache: 111 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus) 112 else: 113 test_sys.cpu[i].connectMemPorts(test_sys.membus) 114 115if len(bm) == 2: | 102np = options.num_cpus 103 104if options.l2cache: 105 test_sys.l2 = L2Cache(size = '2MB') 106 test_sys.tol2bus = Bus() 107 test_sys.l2.cpu_side = test_sys.tol2bus.port 108 test_sys.l2.mem_side = test_sys.membus.port 109 --- 4 unchanged lines hidden (view full) --- 114 L1Cache(size = '64kB')) 115 116 if options.l2cache: 117 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus) 118 else: 119 test_sys.cpu[i].connectMemPorts(test_sys.membus) 120 121if len(bm) == 2: |
116 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) | 122 if m5.build_env['TARGET_ISA'] == 'alpha': 123 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 124 elif m5.build_env['TARGET_ISA'] == 'sparc': 125 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) |
117 drive_sys.cpu = DriveCPUClass(cpu_id=0) 118 drive_sys.cpu.connectMemPorts(drive_sys.membus) 119 root = makeDualRoot(test_sys, drive_sys, options.etherdump) 120elif len(bm) == 1: 121 root = Root(clock = '1THz', system = test_sys) 122else: 123 print "Error I don't know how to create more than 2 systems." 124 sys.exit(1) 125 126Simulation.run(options, root, test_sys, FutureClass) | 126 drive_sys.cpu = DriveCPUClass(cpu_id=0) 127 drive_sys.cpu.connectMemPorts(drive_sys.membus) 128 root = makeDualRoot(test_sys, drive_sys, options.etherdump) 129elif len(bm) == 1: 130 root = Root(clock = '1THz', system = test_sys) 131else: 132 print "Error I don't know how to create more than 2 systems." 133 sys.exit(1) 134 135Simulation.run(options, root, test_sys, FutureClass) |