fs.py (3448:bb2632fa57dc) fs.py (3476:0e26b5458236)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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102test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
103np = options.num_cpus
104test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
105for i in xrange(np):
106 if options.caches and not options.standard_switch:
107 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
108 L1Cache(size = '64kB'))
109 test_sys.cpu[i].connectMemPorts(test_sys.membus)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 93 unchanged lines hidden (view full) ---

102test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
103np = options.num_cpus
104test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
105for i in xrange(np):
106 if options.caches and not options.standard_switch:
107 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
108 L1Cache(size = '64kB'))
109 test_sys.cpu[i].connectMemPorts(test_sys.membus)
110 test_sys.cpu[i].mem = test_sys.physmem
111
112if len(bm) == 2:
113 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
114 drive_sys.cpu = DriveCPUClass(cpu_id=0)
115 drive_sys.cpu.connectMemPorts(drive_sys.membus)
110
111if len(bm) == 2:
112 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
113 drive_sys.cpu = DriveCPUClass(cpu_id=0)
114 drive_sys.cpu.connectMemPorts(drive_sys.membus)
116 drive_sys.cpu.mem = drive_sys.physmem
117 root = makeDualRoot(test_sys, drive_sys, options.etherdump)
118elif len(bm) == 1:
119 root = Root(clock = '1THz', system = test_sys)
120else:
121 print "Error I don't know how to create more than 2 systems."
122 sys.exit(1)
123
124Simulation.run(options, root, test_sys)
115 root = makeDualRoot(test_sys, drive_sys, options.etherdump)
116elif len(bm) == 1:
117 root = Root(clock = '1THz', system = test_sys)
118else:
119 print "Error I don't know how to create more than 2 systems."
120 sys.exit(1)
121
122Simulation.run(options, root, test_sys)