fs.py (3398:7f14cadf3afd) fs.py (3402:db60546818d0)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 123 unchanged lines hidden (view full) ---

132test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
133np = options.num_cpus
134test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
135for i in xrange(np):
136 if options.caches and not options.standard_switch:
137 test_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
138 MyCache(size = '64kB'))
139 test_sys.cpu[i].connectMemPorts(test_sys.membus)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 123 unchanged lines hidden (view full) ---

132test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
133np = options.num_cpus
134test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
135for i in xrange(np):
136 if options.caches and not options.standard_switch:
137 test_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
138 MyCache(size = '64kB'))
139 test_sys.cpu[i].connectMemPorts(test_sys.membus)
140 test_sys.cpu[i].mem = test_sys.physmem
141
142if len(bm) == 2:
143 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
144 drive_sys.cpu = DriveCPUClass(cpu_id=0)
145 drive_sys.cpu.connectMemPorts(drive_sys.membus)
140
141if len(bm) == 2:
142 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
143 drive_sys.cpu = DriveCPUClass(cpu_id=0)
144 drive_sys.cpu.connectMemPorts(drive_sys.membus)
146 drive_sys.cpu.mem = drive_sys.physmem
147 root = makeDualRoot(test_sys, drive_sys, options.etherdump)
148elif len(bm) == 1:
149 root = Root(clock = '1THz', system = test_sys)
150else:
151 print "Error I don't know how to create more than 2 systems."
152 sys.exit(1)
153
154if options.standard_switch:
155 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)]
156 switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) for i in xrange(np)]
157 for i in xrange(np):
158 switch_cpus[i].system = test_sys
159 switch_cpus1[i].system = test_sys
160 switch_cpus[i].clock = TestCPUClass.clock
161 switch_cpus1[i].clock = TestCPUClass.clock
162 if options.caches:
163 switch_cpus[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
164 MyCache(size = '64kB'))
165
145 root = makeDualRoot(test_sys, drive_sys, options.etherdump)
146elif len(bm) == 1:
147 root = Root(clock = '1THz', system = test_sys)
148else:
149 print "Error I don't know how to create more than 2 systems."
150 sys.exit(1)
151
152if options.standard_switch:
153 switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)]
154 switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) for i in xrange(np)]
155 for i in xrange(np):
156 switch_cpus[i].system = test_sys
157 switch_cpus1[i].system = test_sys
158 switch_cpus[i].clock = TestCPUClass.clock
159 switch_cpus1[i].clock = TestCPUClass.clock
160 if options.caches:
161 switch_cpus[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
162 MyCache(size = '64kB'))
163
166 switch_cpus[i].mem = test_sys.physmem
167 switch_cpus1[i].mem = test_sys.physmem
168 switch_cpus[i].connectMemPorts(test_sys.membus)
169 root.switch_cpus = switch_cpus
170 root.switch_cpus1 = switch_cpus1
171 switch_cpu_list = [(test_sys.cpu[i], switch_cpus[i]) for i in xrange(np)]
172 switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)]
173
174m5.instantiate(root)
175

--- 104 unchanged lines hidden --- 		164 switch_cpus[i].connectMemPorts(test_sys.membus)
165 root.switch_cpus = switch_cpus
166 root.switch_cpus1 = switch_cpus1
167 switch_cpu_list = [(test_sys.cpu[i], switch_cpus[i]) for i in xrange(np)]
168 switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)]
169
170m5.instantiate(root)
171

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