| fs.py (13684:076506a21535) | fs.py (13731:67cd980cb20f) |
|---|---|
| 1# Copyright (c) 2010-2013, 2016, 2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 124 unchanged lines hidden (view full) --- 133 134 if options.virtualisation: 135 test_sys.have_virtualization = True 136 137 test_sys.init_param = options.init_param 138 139 # For now, assign all the CPUs to the same clock domain 140 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) | 1# Copyright (c) 2010-2013, 2016, 2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 124 unchanged lines hidden (view full) --- 133 134 if options.virtualisation: 135 test_sys.have_virtualization = True 136 137 test_sys.init_param = options.init_param 138 139 # For now, assign all the CPUs to the same clock domain 140 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) |
| 141 for i in xrange(np)] | 141 for i in range(np)] |
| 142 143 if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 144 test_sys.kvm_vm = KvmVM() 145 146 if options.ruby: 147 bootmem = getattr(test_sys, 'bootmem', None) 148 Ruby.create_system(options, True, test_sys, test_sys.iobus, 149 test_sys._dma_ports, bootmem) --- 39 unchanged lines hidden (view full) --- 189 190 # Sanity check 191 if options.simpoint_profile: 192 if not CpuConfig.is_noncaching_cpu(TestCPUClass): 193 fatal("SimPoint generation should be done with atomic cpu") 194 if np > 1: 195 fatal("SimPoint generation not supported with more than one CPUs") 196 | 142 143 if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 144 test_sys.kvm_vm = KvmVM() 145 146 if options.ruby: 147 bootmem = getattr(test_sys, 'bootmem', None) 148 Ruby.create_system(options, True, test_sys, test_sys.iobus, 149 test_sys._dma_ports, bootmem) --- 39 unchanged lines hidden (view full) --- 189 190 # Sanity check 191 if options.simpoint_profile: 192 if not CpuConfig.is_noncaching_cpu(TestCPUClass): 193 fatal("SimPoint generation should be done with atomic cpu") 194 if np > 1: 195 fatal("SimPoint generation not supported with more than one CPUs") 196 |
| 197 for i in xrange(np): | 197 for i in range(np): |
| 198 if options.simpoint_profile: 199 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 200 if options.checker: 201 test_sys.cpu[i].addCheckerCpu() 202 if options.bp_type: 203 bpClass = BPConfig.get(options.bp_type) 204 test_sys.cpu[i].branchPred = bpClass() 205 test_sys.cpu[i].createThreads() --- 66 unchanged lines hidden (view full) --- 272 ranges = drive_sys.mem_ranges) 273 drive_sys.iobridge.slave = drive_sys.iobus.master 274 drive_sys.iobridge.master = drive_sys.membus.slave 275 276 # Create the appropriate memory controllers and connect them to the 277 # memory bus 278 drive_sys.mem_ctrls = [DriveMemClass(range = r) 279 for r in drive_sys.mem_ranges] | 198 if options.simpoint_profile: 199 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 200 if options.checker: 201 test_sys.cpu[i].addCheckerCpu() 202 if options.bp_type: 203 bpClass = BPConfig.get(options.bp_type) 204 test_sys.cpu[i].branchPred = bpClass() 205 test_sys.cpu[i].createThreads() --- 66 unchanged lines hidden (view full) --- 272 ranges = drive_sys.mem_ranges) 273 drive_sys.iobridge.slave = drive_sys.iobus.master 274 drive_sys.iobridge.master = drive_sys.membus.slave 275 276 # Create the appropriate memory controllers and connect them to the 277 # memory bus 278 drive_sys.mem_ctrls = [DriveMemClass(range = r) 279 for r in drive_sys.mem_ranges] |
| 280 for i in xrange(len(drive_sys.mem_ctrls)): | 280 for i in range(len(drive_sys.mem_ctrls)): |
| 281 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 282 283 drive_sys.init_param = options.init_param 284 285 return drive_sys 286 287# Add options 288parser = optparse.OptionParser() --- 81 unchanged lines hidden --- | 281 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 282 283 drive_sys.init_param = options.init_param 284 285 return drive_sys 286 287# Add options 288parser = optparse.OptionParser() --- 81 unchanged lines hidden --- |