fs.py (13432:6ce67b7e6e44) fs.py (13606:2ad4449e6cb4)
1# Copyright (c) 2010-2013, 2016 ARM Limited
1# Copyright (c) 2010-2013, 2016, 2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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90 elif buildEnv['TARGET_ISA'] == "x86":
91 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
92 options.ruby, cmdline=cmdline)
93 elif buildEnv['TARGET_ISA'] == "arm":
94 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
95 options.num_cpus, bm[0], options.dtb_filename,
96 bare_metal=options.bare_metal,
97 cmdline=cmdline,
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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90 elif buildEnv['TARGET_ISA'] == "x86":
91 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
92 options.ruby, cmdline=cmdline)
93 elif buildEnv['TARGET_ISA'] == "arm":
94 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
95 options.num_cpus, bm[0], options.dtb_filename,
96 bare_metal=options.bare_metal,
97 cmdline=cmdline,
98 ignore_dtb=options.generate_dtb,
99 external_memory=
100 options.external_memory_system,
101 ruby=options.ruby,
102 security=options.enable_security_extensions)
103 if options.enable_context_switch_stats_dump:
104 test_sys.enable_context_switch_stats_dump = True
105 else:
106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])

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236 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
237 elif buildEnv['TARGET_ISA'] == 'sparc':
238 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
239 elif buildEnv['TARGET_ISA'] == 'x86':
240 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
241 cmdline=cmdline)
242 elif buildEnv['TARGET_ISA'] == 'arm':
243 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
98 external_memory=
99 options.external_memory_system,
100 ruby=options.ruby,
101 security=options.enable_security_extensions)
102 if options.enable_context_switch_stats_dump:
103 test_sys.enable_context_switch_stats_dump = True
104 else:
105 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])

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235 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
236 elif buildEnv['TARGET_ISA'] == 'sparc':
237 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
238 elif buildEnv['TARGET_ISA'] == 'x86':
239 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
240 cmdline=cmdline)
241 elif buildEnv['TARGET_ISA'] == 'arm':
242 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
244 bm[1], options.dtb_filename, cmdline=cmdline,
245 ignore_dtb=options.generate_dtb)
243 bm[1], options.dtb_filename, cmdline=cmdline)
246
247 # Create a top-level voltage domain
248 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
249
250 # Create a source clock for the system and set the clock period
251 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
252 voltage_domain = drive_sys.voltage_domain)
253

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349 sys.exit(1)
350
351if options.timesync:
352 root.time_sync_enable = True
353
354if options.frame_capture:
355 VncServer.frame_capture = True
356
244
245 # Create a top-level voltage domain
246 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
247
248 # Create a source clock for the system and set the clock period
249 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
250 voltage_domain = drive_sys.voltage_domain)
251

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347 sys.exit(1)
348
349if options.timesync:
350 root.time_sync_enable = True
351
352if options.frame_capture:
353 VncServer.frame_capture = True
354
357if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb:
358 # Sanity checks
359 if options.dtb_filename:
360 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\
361 "same time.")
362
355if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \
356 and not options.dtb_filename:
363 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
364 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
365 "platforms, unless custom hardware models have been equipped "\
366 "with generation functionality.")
367
368 # Generate a Device Tree
369 def create_dtb_for_system(system, filename):
370 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)

--- 14 unchanged lines hidden --- 		357 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
358 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
359 "platforms, unless custom hardware models have been equipped "\
360 "with generation functionality.")
361
362 # Generate a Device Tree
363 def create_dtb_for_system(system, filename):
364 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)

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